mirror of
https://github.com/firewalkwithm3/qmk_firmware.git
synced 2024-11-23 03:50:28 +08:00
63 lines
2 KiB
Plaintext
63 lines
2 KiB
Plaintext
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Time to Sleep
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=============
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USB suspend no activity on USB line for 3ms
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No Interaction no user interaction
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matrix has no change
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matrix has no switch on
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AVR Power Management
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====================
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V-USB suspend
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USB suspend
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http://vusb.wikidot.com/examples
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MCUSR MCU Status Register
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WDRF Watchdog Reset Flag
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BORF
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EXTRF
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PORF Power-on Reset Flag
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SMCR Sleep Mode Control Register
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SE Sleep Enable
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SM2:0
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#define set_sleep_mode(mode) \
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#define SLEEP_MODE_IDLE (0)
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#define SLEEP_MODE_ADC _BV(SM0)
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#define SLEEP_MODE_PWR_DOWN _BV(SM1)
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#define SLEEP_MODE_PWR_SAVE (_BV(SM0) | _BV(SM1))
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#define SLEEP_MODE_STANDBY (_BV(SM1) | _BV(SM2))
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#define SLEEP_MODE_EXT_STANDBY (_BV(SM0) | _BV(SM1) | _BV(SM2))
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ACSR Analog Comparator Control and Status Register
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To disable Analog Comparator
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ACSR = 0x80;
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or
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ACSR &= ~_BV(ACIE);
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ACSR |= _BV(ACD);
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ACD: Analog Comparator Disable
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When this bit is written logic one, the power to the Analog Comparator is
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switched off. This bit can be set at any time to turn off the Analog
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Comparator. This will reduce power consumption in Active and Idle mode.
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When changing the ACD bit, the Analog Comparator Interrupt must be disabled
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by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when
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the bit is changed.
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DIDR1 Digital Input Disable Register 1
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AIN1D
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AIN0D
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When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corresponding PIN Register bit will always read as zero when this bit is set. When an analog signal is applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer.
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PRR Power Reduction Register
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PRTWI
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PRTIM2
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PRTIM0
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PRTIM1
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PRSPI
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PRUSART0
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PRADC
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