fern/sensor-watch
1
0
Fork 0
mirror of https://github.com/firewalkwithm3/Sensor-Watch.git synced 2024-11-22 11:10:29 +08:00
Code Issues Actions Packages Projects Releases Wiki Activity

major project reorg, move library one level up

Browse source
This commit is contained in:
Joey Castillo 2021-08-02 13:48:35 -04:00
parent 2d1e2e8c76
commit 34945d78e9
439 changed files with 75 additions and 108488 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

0
Sensor Watch Starter Project/app/app.c → Sensor Watch Starter Project/app.c
View file

0
Sensor Watch Starter Project/app/app.h → Sensor Watch Starter Project/app.h
View file

144
Sensor Watch Starter Project/make/Makefile
View file

@ -8,7 +8,7 @@ BIN = watch
CC = arm-none-eabi-gcc
OBJCOPY = arm-none-eabi-objcopy
SIZE = arm-none-eabi-size
UF2 = python uf2conv.py
UF2 = python ../../utils/uf2conv.py
ifeq ($(OS), Windows_NT)
MKDIR = gmkdir
@ -25,79 +25,83 @@ CFLAGS += -MD -MP -MT $(BUILD)/$(*F).o -MF $(BUILD)/$(@F).d
LDFLAGS += -mcpu=cortex-m0plus -mthumb
LDFLAGS += -Wl,--gc-sections
LDFLAGS += -Wl,--script=../linker/saml22j18.ld
LDFLAGS += -Wl,--script=../../watch-library/linker/saml22j18.ld
# If you add any additional directories with headers, add them to this list, e.g.
# ../drivers/
INCLUDES += \
-I../include \
-I../hal/ \
-I../hal/documentation/ \
-I../hal/include/ \
-I../hal/src/ \
-I../hal/utils/ \
-I../hal/utils/include/ \
-I../hal/utils/src/ \
-I../hpl/ \
-I../hpl/adc/ \
-I../hpl/core/ \
-I../hpl/dmac/ \
-I../hpl/eic/ \
-I../hpl/gclk/ \
-I../hpl/mclk/ \
-I../hpl/osc32kctrl/ \
-I../hpl/oscctrl/ \
-I../hpl/pm/ \
-I../hpl/port/ \
-I../hpl/rtc/ \
-I../hpl/sercom/ \
-I../hpl/slcd/ \
-I../hpl/systick/ \
-I../hpl/tcc/ \
-I../hpl/tc/ \
-I../hri/ \
-I../config/ \
-I../hw/ \
-I../watch/ \
-I../app/ \
-I..
-I../ \
-I../../watch-library/include \
-I../../watch-library/hal/ \
-I../../watch-library/hal/documentation/ \
-I../../watch-library/hal/include/ \
-I../../watch-library/hal/src/ \
-I../../watch-library/hal/utils/ \
-I../../watch-library/hal/utils/include/ \
-I../../watch-library/hal/utils/src/ \
-I../../watch-library/hpl/ \
-I../../watch-library/hpl/adc/ \
-I../../watch-library/hpl/core/ \
-I../../watch-library/hpl/dmac/ \
-I../../watch-library/hpl/eic/ \
-I../../watch-library/hpl/gclk/ \
-I../../watch-library/hpl/mclk/ \
-I../../watch-library/hpl/osc32kctrl/ \
-I../../watch-library/hpl/oscctrl/ \
-I../../watch-library/hpl/pm/ \
-I../../watch-library/hpl/port/ \
-I../../watch-library/hpl/rtc/ \
-I../../watch-library/hpl/sercom/ \
-I../../watch-library/hpl/slcd/ \
-I../../watch-library/hpl/systick/ \
-I../../watch-library/hpl/tcc/ \
-I../../watch-library/hpl/tc/ \
-I../../watch-library/hri/ \
-I../../watch-library/config/ \
-I../../watch-library/hw/ \
-I../../watch-library/watch/ \
-I../../watch-library
# If you add any additional C files to your project, add them each to this list, e.g.
# ../drivers/st25dv.c
SRCS += \
../main.c \
../startup_saml22.c \
../hw/driver_init.c \
../watch/watch.c \
../app/app.c \
../hal/src/hal_adc_sync.c \
../hal/src/hal_atomic.c \
../hal/src/hal_calendar.c \
../hal/src/hal_delay.c \
../hal/src/hal_ext_irq.c \
../hal/src/hal_gpio.c \
../hal/src/hal_i2c_m_sync.c \
../hal/src/hal_init.c \
../hal/src/hal_io.c \
../hal/src/hal_pwm.c \
../hal/src/hal_slcd_sync.c \
../hal/src/hal_sleep.c \
../hal/utils/src/utils_assert.c \
../hal/utils/src/utils_event.c \
../hal/utils/src/utils_list.c \
../hal/utils/src/utils_syscalls.c \
../hpl/adc/hpl_adc.c \
../hpl/core/hpl_core_m0plus_base.c \
../hpl/core/hpl_init.c \
../hpl/dmac/hpl_dmac.c \
../hpl/eic/hpl_eic.c \
../hpl/gclk/hpl_gclk.c \
../hpl/mclk/hpl_mclk.c \
../hpl/osc32kctrl/hpl_osc32kctrl.c \
../hpl/oscctrl/hpl_oscctrl.c \
../hpl/pm/hpl_pm.c \
../hpl/rtc/hpl_rtc.c \
../hpl/sercom/hpl_sercom.c \
../hpl/slcd/hpl_slcd.c \
../hpl/systick/hpl_systick.c \
../hpl/tcc/hpl_tcc.c \
../hpl/tc/hpl_tc.c
../app.c \
../../watch-library/main.c \
../../watch-library/startup_saml22.c \
../../watch-library/hw/driver_init.c \
../../watch-library/watch/watch.c \
../../watch-library/hal/src/hal_adc_sync.c \
../../watch-library/hal/src/hal_atomic.c \
../../watch-library/hal/src/hal_calendar.c \
../../watch-library/hal/src/hal_delay.c \
../../watch-library/hal/src/hal_ext_irq.c \
../../watch-library/hal/src/hal_gpio.c \
../../watch-library/hal/src/hal_i2c_m_sync.c \
../../watch-library/hal/src/hal_init.c \
../../watch-library/hal/src/hal_io.c \
../../watch-library/hal/src/hal_pwm.c \
../../watch-library/hal/src/hal_slcd_sync.c \
../../watch-library/hal/src/hal_sleep.c \
../../watch-library/hal/utils/src/utils_assert.c \
../../watch-library/hal/utils/src/utils_event.c \
../../watch-library/hal/utils/src/utils_list.c \
../../watch-library/hal/utils/src/utils_syscalls.c \
../../watch-library/hpl/adc/hpl_adc.c \
../../watch-library/hpl/core/hpl_core_m0plus_base.c \
../../watch-library/hpl/core/hpl_init.c \
../../watch-library/hpl/dmac/hpl_dmac.c \
../../watch-library/hpl/eic/hpl_eic.c \
../../watch-library/hpl/gclk/hpl_gclk.c \
../../watch-library/hpl/mclk/hpl_mclk.c \
../../watch-library/hpl/osc32kctrl/hpl_osc32kctrl.c \
../../watch-library/hpl/oscctrl/hpl_oscctrl.c \
../../watch-library/hpl/pm/hpl_pm.c \
../../watch-library/hpl/rtc/hpl_rtc.c \
../../watch-library/hpl/sercom/hpl_sercom.c \
../../watch-library/hpl/slcd/hpl_slcd.c \
../../watch-library/hpl/systick/hpl_systick.c \
../../watch-library/hpl/tcc/hpl_tcc.c \
../../watch-library/hpl/tc/hpl_tc.c
DEFINES += \
-D__SAML22J18A__ \

6
Smol Watch Project/My Project/.atmelstart/AtmelStart.env_conf
View file

@ -1,6 +0,0 @@
<environment>
<configurations/>
<device-packs>
<device-pack device="ATSAML22J18A" name="SAML22_DFP" vendor="Atmel" version="1.2.77"/>
</device-packs>
</environment>

233
Smol Watch Project/My Project/.atmelstart/AtmelStart.gpdsc
View file

@ -1,233 +0,0 @@
<package xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" schemaVersion="1.0" xs:noNamespaceSchemaLocation="PACK.xsd">
<vendor>Atmel</vendor>
<name>My Project</name>
<description>Project generated by Atmel Start</description>
<url>http://start.atmel.com/</url>
<releases>
<release version="1.0.1">Initial version</release>
</releases>
<taxonomy>
<description Cclass="AtmelStart" generator="AtmelStart">Configuration Files generated by Atmel Start</description>
</taxonomy>
<generators>
<generator id="AtmelStart">
<description>Atmel Start</description>
<select Dname="ATSAML22J18A" Dvendor="Atmel:3"/>
<command>http://start.atmel.com/</command>
<files>
<file category="generator" name="atmel_start_config.atstart"/>
<file attr="template" category="other" name="AtmelStart.env_conf" select="Environment configuration"/>
</files>
</generator>
</generators>
<conditions>
<condition id="CMSIS Device Startup">
<description>Dependency on CMSIS core and Device Startup components</description>
<require Cclass="CMSIS" Cgroup="CORE" Cversion="5.1.2"/>
<require Cclass="Device" Cgroup="Startup" Cversion="1.2.0"/>
</condition>
<condition id="ARMCC, GCC, IAR">
<require Dname="ATSAML22J18A"/>
<accept Tcompiler="ARMCC"/>
<accept Tcompiler="GCC"/>
<accept Tcompiler="IAR"/>
</condition>
<condition id="GCC">
<require Dname="ATSAML22J18A"/>
<accept Tcompiler="GCC"/>
</condition>
</conditions>
<components generator="AtmelStart">
<component Cclass="AtmelStart" Cgroup="Framework" Cversion="1.0.0" condition="CMSIS Device Startup">
<description>Atmel Start Framework</description>
<RTE_Components_h>#define ATMEL_START</RTE_Components_h>
<files>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/adc_sync.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/calendar.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/ext_irq.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/i2c_master_sync.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/pwm.rst"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hal/documentation/slcd_sync.rst"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_atomic.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_calendar.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_delay.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_ext_irq.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_gpio.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_i2c_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_io.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_slcd_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_sleep.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_core.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_delay.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_ext_irq.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_gpio.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_i2c_s_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_irq.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_slcd.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_slcd_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_sleep.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_time_measure.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_atomic.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_delay.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_gpio.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_i2c_m_sync.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_init.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_io.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_slcd_sync.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_sleep.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/compiler.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/err_codes.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/events.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_assert.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_decrement_macro.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_event.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_increment_macro.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_list.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_recursion_macro.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/utils_repeat_macro.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_assert.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_event.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/utils/src/utils_list.c"/>
<file category="source" condition="GCC" name="hal/utils/src/utils_syscalls.c"/>
<file category="doc" condition="ARMCC, GCC, IAR" name="hpl/doc_lite/tc.rst"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/slcd/hpl_slcd.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/slcd/hpl_slcd_cm.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ac_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_adc_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_aes_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_ccl_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dmac_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_dsu_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_eic_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_evsys_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_freqm_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_gclk_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mclk_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_mtb_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvic_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_nvmctrl_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_osc32kctrl_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_oscctrl_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pac_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_pm_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_port_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rstc_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_rtc_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_sercom_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_slcd_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_supc_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_systemcontrol_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_systick_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tc_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_tcc_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_trng_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_usb_l22.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hri/hri_wdt_l22.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="main.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="driver_init.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="driver_init.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start_pins.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="examples/driver_examples.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="examples/driver_examples.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_adc_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hal_pwm.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_adc_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_calendar.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_missing_features.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_pwm.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_reset.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_dma.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_m_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_spi_s_sync.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_timer.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_async.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/include/hpl_usart_sync.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_adc_sync.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_calendar.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_ext_irq.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hal/src/hal_pwm.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hal/utils/include/parts.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/adc/hpl_adc_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_m0plus_base.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_core_port.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/core/hpl_init.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/dmac/hpl_dmac.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/eic/hpl_eic.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/gclk/hpl_gclk_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/mclk/hpl_mclk.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl/hpl_osc32kctrl.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/oscctrl/hpl_oscctrl.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/pm/hpl_pm_base.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/port/hpl_gpio_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/rtc/hpl_rtc.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/rtc/hpl_rtc_base.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/sercom/hpl_sercom.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/slcd/hpl_slcd_cm_14_seg_mapping.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/slcd/hpl_slcd_cm_7_seg_mapping.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/systick/hpl_systick.c"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tc/tc_lite.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.c"/>
<file category="header" condition="ARMCC, GCC, IAR" name="hpl/tcc/hpl_tcc.h"/>
<file category="header" condition="ARMCC, GCC, IAR" name="atmel_start.h"/>
<file category="source" condition="ARMCC, GCC, IAR" name="atmel_start.c"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_adc_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_dmac_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_eic_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_gclk_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_mclk_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_osc32kctrl_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_oscctrl_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_port_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_rtc_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_sercom_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_slcd_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_systick_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/hpl_tcc_config.h"/>
<file attr="config" category="header" condition="ARMCC, GCC, IAR" name="config/peripheral_clk_config.h"/>
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
<file category="include" condition="ARMCC, GCC, IAR" name="config"/>
<file category="include" condition="ARMCC, GCC, IAR" name="examples"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hal/include"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hal/utils/include"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/adc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/core"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/dmac"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/eic"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/gclk"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/mclk"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/osc32kctrl"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/oscctrl"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/pm"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/port"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/rtc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/sercom"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/slcd"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/systick"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/tc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hpl/tcc"/>
<file category="include" condition="ARMCC, GCC, IAR" name="hri"/>
<file category="include" condition="ARMCC, GCC, IAR" name=""/>
</files>
</component>
</components>
</package>

1717
Smol Watch Project/My Project/.atmelstart/atmel_start_config.atstart
View file

File diff suppressed because it is too large Load diff

54
Smol Watch Project/My Project/Config/RTE_Components.h
View file

@ -1,54 +0,0 @@
/**
* \file
*
* \brief Autogenerated API include file for the Atmel Configuration Management Engine (ACME)
*
* Copyright (c) 2012 Atmel Corporation. All rights reserved.
*
* \acme_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \acme_license_stop
*
* Project: My Project
* Target: ATSAML22J18A
*
**/
#ifndef RTE_COMPONENTS_H
#define RTE_COMPONENTS_H
#define ATMEL_START
#endif /* RTE_COMPONENTS_H */

305
Smol Watch Project/My Project/Config/hpl_adc_config.h
View file

@ -1,305 +0,0 @@
/* Auto-generated config file hpl_adc_config.h */
#ifndef HPL_ADC_CONFIG_H
#define HPL_ADC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#ifndef CONF_ADC_0_ENABLE
#define CONF_ADC_0_ENABLE 1
#endif
// <h> Basic Configuration
// <o> Conversion Result Resolution
// <0x0=>12-bit
// <0x1=>16-bit (averaging must be enabled)
// <0x2=>10-bit
// <0x3=>8-bit
// <i> Defines the bit resolution for the ADC sample values (RESSEL)
// <id> adc_resolution
#ifndef CONF_ADC_0_RESSEL
#define CONF_ADC_0_RESSEL 0x0
#endif
// <o> Reference Selection
// <0x0=>Internal bandgap reference
// <0x1=>1/1.6 VDDANA
// <0x2=>1/2 VDDANA (only for VDDANA > 2.0V)
// <0x3=>External reference A
// <0x4=>External reference B
// <0x5=>VDDANA
// <i> Select the reference for the ADC (REFSEL)
// <id> adc_reference
#ifndef CONF_ADC_0_REFSEL
#define CONF_ADC_0_REFSEL 0x0
#endif
// <o> Prescaler configuration
// <0x0=>Peripheral clock divided by 2
// <0x1=>Peripheral clock divided by 4
// <0x2=>Peripheral clock divided by 8
// <0x3=>Peripheral clock divided by 16
// <0x4=>Peripheral clock divided by 32
// <0x5=>Peripheral clock divided by 64
// <0x6=>Peripheral clock divided by 128
// <0x7=>Peripheral clock divided by 256
// <i> These bits define the ADC clock relative to the peripheral clock (PRESCALER)
// <id> adc_prescaler
#ifndef CONF_ADC_0_PRESCALER
#define CONF_ADC_0_PRESCALER 0x0
#endif
// <q> Free Running Mode
// <i> When enabled, the ADC is in free running mode and a new conversion will be initiated when a previous conversion completes. (FREERUN)
// <id> adc_freerunning_mode
#ifndef CONF_ADC_0_FREERUN
#define CONF_ADC_0_FREERUN 0
#endif
// <q> Differential Mode
// <i> In differential mode, the voltage difference between the MUXPOS and MUXNEG inputs will be converted by the ADC. (DIFFMODE)
// <id> adc_differential_mode
#ifndef CONF_ADC_0_DIFFMODE
#define CONF_ADC_0_DIFFMODE 0
#endif
// <o> Positive Mux Input Selection
// <0x00=>ADC AIN0 pin
// <0x01=>ADC AIN1 pin
// <0x02=>ADC AIN2 pin
// <0x03=>ADC AIN3 pin
// <0x04=>ADC AIN4 pin
// <0x05=>ADC AIN5 pin
// <0x06=>ADC AIN6 pin
// <0x07=>ADC AIN7 pin
// <0x08=>ADC AIN8 pin
// <0x09=>ADC AIN9 pin
// <0x0A=>ADC AIN10 pin
// <0x0B=>ADC AIN11 pin
// <0x0C=>ADC AIN12 pin
// <0x0D=>ADC AIN13 pin
// <0x0E=>ADC AIN14 pin
// <0x0F=>ADC AIN15 pin
// <0x10=>ADC AIN16 pin
// <0x11=>ADC AIN17 pin
// <0x12=>ADC AIN18 pin
// <0x13=>ADC AIN19 pin
// <0x18=>Temperature reference
// <0x19=>Bandgap voltage
// <0x1A=>1/4 scaled core supply
// <0x1B=>1/4 scaled I/O supply
// <0x1D=>1/4 Scaled VBAT Supply
// <0x1E=>CTAT Output
// <i> These bits define the Mux selection for the positive ADC input. (MUXPOS)
// <id> adc_pinmux_positive
#ifndef CONF_ADC_0_MUXPOS
#define CONF_ADC_0_MUXPOS 0x0
#endif
// <o> Negative Mux Input Selection
// <0x00=>ADC AIN0 pin
// <0x01=>ADC AIN1 pin
// <0x02=>ADC AIN2 pin
// <0x03=>ADC AIN3 pin
// <0x04=>ADC AIN4 pin
// <0x05=>ADC AIN5 pin
// <0x06=>ADC AIN6 pin
// <0x07=>ADC AIN7 pin
// <0x18=>Internal ground
// <i> These bits define the Mux selection for the negative ADC input. (MUXNEG)
// <id> adc_pinmux_negative
#ifndef CONF_ADC_0_MUXNEG
#define CONF_ADC_0_MUXNEG 0x0
#endif
// </h>
// <e> Advanced Configuration
// <id> adc_advanced_settings
#ifndef CONF_ADC_0_ADVANCED
#define CONF_ADC_0_ADVANCED 0
#endif
// <q> Run in standby
// <i> Indicates whether the ADC will continue running in standby sleep mode or not (RUNSTDBY)
// <id> adc_arch_runstdby
#ifndef CONF_ADC_0_RUNSTDBY
#define CONF_ADC_0_RUNSTDBY 0
#endif
// <q>Debug Run
// <i> If enabled, the ADC is running if the CPU is halted by an external debugger. (DBGRUN)
// <id> adc_arch_dbgrun
#ifndef CONF_ADC_0_DBGRUN
#define CONF_ADC_0_DBGRUN 0
#endif
// <q> On Demand Control
// <i> Will keep the ADC peripheral running if requested by other peripherals (ONDEMAND)
// <id> adc_arch_ondemand
#ifndef CONF_ADC_0_ONDEMAND
#define CONF_ADC_0_ONDEMAND 0
#endif
// <q> Left-Adjusted Result
// <i> When enabled, the ADC conversion result is left-adjusted in the RESULT register. The high byte of the 12-bit result will be present in the upper part of the result register. (LEFTADJ)
// <id> adc_arch_leftadj
#ifndef CONF_ADC_0_LEFTADJ
#define CONF_ADC_0_LEFTADJ 0
#endif
// <q> Reference Buffer Offset Compensation Enable
// <i> The accuracy of the gain stage can be increased by enabling the reference buffer offset compensation. This will decrease the input impedance and thus increase the start-up time of the reference. (REFCOMP)
// <id> adc_arch_refcomp
#ifndef CONF_ADC_0_REFCOMP
#define CONF_ADC_0_REFCOMP 0
#endif
// <q>Comparator Offset Compensation Enable
// <i> This bit indicates whether the Comparator Offset Compensation is enabled or not (OFFCOMP)
// <id> adc_arch_offcomp
#ifndef CONF_ADC_0_OFFCOMP
#define CONF_ADC_0_OFFCOMP 0
#endif
// <q> Digital Correction Logic Enabled
// <i> When enabled, the ADC conversion result in the RESULT register is then corrected for gain and offset based on the values in the GAINCAL and OFFSETCAL registers. (CORREN)
// <id> adc_arch_corren
#ifndef CONF_ADC_0_CORREN
#define CONF_ADC_0_CORREN 0
#endif
// <o> Offset Correction Value <0-4095>
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for offset error before being written to the Result register. (OFFSETCORR)
// <id> adc_arch_offsetcorr
#ifndef CONF_ADC_0_OFFSETCORR
#define CONF_ADC_0_OFFSETCORR 0
#endif
// <o> Gain Correction Value <0-4095>
// <i> If the digital correction logic is enabled (CTRLB.CORREN = 1), these bits define how the ADC conversion result is compensated for gain error before being written to the result register. (GAINCORR)
// <id> adc_arch_gaincorr
#ifndef CONF_ADC_0_GAINCORR
#define CONF_ADC_0_GAINCORR 0
#endif
// <o> Adjusting Result / Division Coefficient <0-7>
// <i> These bits define the division coefficient in 2n steps. (ADJRES)
// <id> adc_arch_adjres
#ifndef CONF_ADC_0_ADJRES
#define CONF_ADC_0_ADJRES 0x0
#endif
// <o.0..10> Number of Samples to be Collected
// <0x0=>1 sample
// <0x1=>2 samples
// <0x2=>4 samples
// <0x3=>8 samples
// <0x4=>16 samples
// <0x5=>32 samples
// <0x6=>64 samples
// <0x7=>128 samples
// <0x8=>256 samples
// <0x9=>512 samples
// <0xA=>1024 samples
// <i> Define how many samples should be added together.The result will be available in the Result register (SAMPLENUM)
// <id> adc_arch_samplenum
#ifndef CONF_ADC_0_SAMPLENUM
#define CONF_ADC_0_SAMPLENUM 0x0
#endif
// <o> Sampling Time Length <0-63>
// <i> These bits control the ADC sampling time in number of CLK_ADC cycles, depending of the prescaler value, thus controlling the ADC input impedance. (SAMPLEN)
// <id> adc_arch_samplen
#ifndef CONF_ADC_0_SAMPLEN
#define CONF_ADC_0_SAMPLEN 0
#endif
// <o> Window Monitor Mode
// <0x0=>No window mode
// <0x1=>Mode 1: RESULT above lower threshold
// <0x2=>Mode 2: RESULT beneath upper threshold
// <0x3=>Mode 3: RESULT inside lower and upper threshold
// <0x4=>Mode 4: RESULT outside lower and upper threshold
// <i> These bits enable and define the window monitor mode. (WINMODE)
// <id> adc_arch_winmode
#ifndef CONF_ADC_0_WINMODE
#define CONF_ADC_0_WINMODE 0x0
#endif
// <o> Window Monitor Lower Threshold <0-65535>
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINLT)
// <id> adc_arch_winlt
#ifndef CONF_ADC_0_WINLT
#define CONF_ADC_0_WINLT 0
#endif
// <o> Window Monitor Upper Threshold <0-65535>
// <i> If the window monitor is enabled, these bits define the lower threshold value. (WINUT)
// <id> adc_arch_winut
#ifndef CONF_ADC_0_WINUT
#define CONF_ADC_0_WINUT 0
#endif
// <o> Bitmask for positive input sequence <0-4294967295>
// <i> Use this parameter to input the bitmask for positive input sequence control (refer to datasheet for the device).
// <id> adc_arch_seqen
#ifndef CONF_ADC_0_SEQEN
#define CONF_ADC_0_SEQEN 0x0
#endif
// </e>
// <e> Event Control
// <id> adc_arch_event_settings
#ifndef CONF_ADC_0_EVENT_CONTROL
#define CONF_ADC_0_EVENT_CONTROL 0
#endif
// <q> Window Monitor Event Out
// <i> Enables event output on window event (WINMONEO)
// <id> adc_arch_winmoneo
#ifndef CONF_ADC_0_WINMONEO
#define CONF_ADC_0_WINMONEO 0
#endif
// <q> Result Ready Event Out
// <i> Enables event output on result ready event (RESRDEO)
// <id> adc_arch_resrdyeo
#ifndef CONF_ADC_0_RESRDYEO
#define CONF_ADC_0_RESRDYEO 0
#endif
// <q> Invert flush Event Signal
// <i> Invert the flush event input signal (FLUSHINV)
// <id> adc_arch_flushinv
#ifndef CONF_ADC_0_FLUSHINV
#define CONF_ADC_0_FLUSHINV 0
#endif
// <q> Trigger Flush On Event
// <i> Trigger an ADC pipeline flush on event (FLUSHEI)
// <id> adc_arch_flushei
#ifndef CONF_ADC_0_FLUSHEI
#define CONF_ADC_0_FLUSHEI 0
#endif
// <q> Invert Start Conversion Event Signal
// <i> Invert the start conversion event input signal (STARTINV)
// <id> adc_arch_startinv
#ifndef CONF_ADC_0_STARTINV
#define CONF_ADC_0_STARTINV 0
#endif
// <q> Trigger Conversion On Event
// <i> Trigger a conversion on event. (STARTEI)
// <id> adc_arch_startei
#ifndef CONF_ADC_0_STARTEI
#define CONF_ADC_0_STARTEI 0
#endif
// </e>
// <<< end of configuration section >>>
#endif // HPL_ADC_CONFIG_H

3122
Smol Watch Project/My Project/Config/hpl_dmac_config.h
View file

File diff suppressed because it is too large Load diff

730
Smol Watch Project/My Project/Config/hpl_eic_config.h
View file

@ -1,730 +0,0 @@
/* Auto-generated config file hpl_eic_config.h */
#ifndef HPL_EIC_CONFIG_H
#define HPL_EIC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic Settings
// <o> Clock Selection
// <i> Indicates which clock used, The EIC can be clocked either by GCLK_EIC when higher frequency than 32KHz is required for filtering or
// <i> either by CLK_ULP32K when power consumption is the priority.
// <0x0=> Clocked by GCLK
// <0x1=> Clocked by ULPOSC32K
// <id> eic_arch_cksel
#ifndef CONF_EIC_CKSEL
#define CONF_EIC_CKSEL 0
#endif
// </h>
// <e> Non-Maskable Interrupt Control
// <id> eic_arch_nmi_ctrl
#ifndef CONF_EIC_ENABLE_NMI_CTRL
#define CONF_EIC_ENABLE_NMI_CTRL 0
#endif
// <q> Non-Maskable Interrupt Filter Enable
// <i> Indicates whether the mon-maskable interrupt filter is enabled or not
// <id> eic_arch_nmifilten
#ifndef CONF_EIC_NMIFILTEN
#define CONF_EIC_NMIFILTEN 0
#endif
// <y> Non-Maskable Interrupt Sense
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines non-maskable interrupt sense
// <id> eic_arch_nmisense
#ifndef CONF_EIC_NMISENSE
#define CONF_EIC_NMISENSE EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> Asynchronous Edge Detection Mode
// <i> Indicates the interrupt detection mode operated synchronously or asynchronousl
// <id> eic_arch_nmiasynch
#ifndef CONF_EIC_NMIASYNCH
#define CONF_EIC_NMIASYNCH 0
#endif
// </e>
// <e> Interrupt 0 Settings
// <id> eic_arch_enable_irq_setting0
#ifndef CONF_EIC_ENABLE_IRQ_SETTING0
#define CONF_EIC_ENABLE_IRQ_SETTING0 0
#endif
// <q> External Interrupt 0 Filter Enable
// <i> Indicates whether the external interrupt 0 filter is enabled or not
// <id> eic_arch_filten0
#ifndef CONF_EIC_FILTEN0
#define CONF_EIC_FILTEN0 0
#endif
// <q> External Interrupt 0 Event Output Enable
// <i> Indicates whether the external interrupt 0 event output is enabled or not
// <id> eic_arch_extinteo0
#ifndef CONF_EIC_EXTINTEO0
#define CONF_EIC_EXTINTEO0 0
#endif
// <y> Input 0 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense0
#ifndef CONF_EIC_SENSE0
#define CONF_EIC_SENSE0 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 0 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 0 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch0
#ifndef CONF_EIC_ASYNCH0
#define CONF_EIC_ASYNCH0 0
#endif
// </e>
// <e> Interrupt 1 Settings
// <id> eic_arch_enable_irq_setting1
#ifndef CONF_EIC_ENABLE_IRQ_SETTING1
#define CONF_EIC_ENABLE_IRQ_SETTING1 0
#endif
// <q> External Interrupt 1 Filter Enable
// <i> Indicates whether the external interrupt 1 filter is enabled or not
// <id> eic_arch_filten1
#ifndef CONF_EIC_FILTEN1
#define CONF_EIC_FILTEN1 0
#endif
// <q> External Interrupt 1 Event Output Enable
// <i> Indicates whether the external interrupt 1 event output is enabled or not
// <id> eic_arch_extinteo1
#ifndef CONF_EIC_EXTINTEO1
#define CONF_EIC_EXTINTEO1 0
#endif
// <y> Input 1 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense1
#ifndef CONF_EIC_SENSE1
#define CONF_EIC_SENSE1 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 1 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 1 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch1
#ifndef CONF_EIC_ASYNCH1
#define CONF_EIC_ASYNCH1 0
#endif
// </e>
// <e> Interrupt 2 Settings
// <id> eic_arch_enable_irq_setting2
#ifndef CONF_EIC_ENABLE_IRQ_SETTING2
#define CONF_EIC_ENABLE_IRQ_SETTING2 0
#endif
// <q> External Interrupt 2 Filter Enable
// <i> Indicates whether the external interrupt 2 filter is enabled or not
// <id> eic_arch_filten2
#ifndef CONF_EIC_FILTEN2
#define CONF_EIC_FILTEN2 0
#endif
// <q> External Interrupt 2 Event Output Enable
// <i> Indicates whether the external interrupt 2 event output is enabled or not
// <id> eic_arch_extinteo2
#ifndef CONF_EIC_EXTINTEO2
#define CONF_EIC_EXTINTEO2 0
#endif
// <y> Input 2 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense2
#ifndef CONF_EIC_SENSE2
#define CONF_EIC_SENSE2 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 2 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 2 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch2
#ifndef CONF_EIC_ASYNCH2
#define CONF_EIC_ASYNCH2 0
#endif
// </e>
// <e> Interrupt 3 Settings
// <id> eic_arch_enable_irq_setting3
#ifndef CONF_EIC_ENABLE_IRQ_SETTING3
#define CONF_EIC_ENABLE_IRQ_SETTING3 0
#endif
// <q> External Interrupt 3 Filter Enable
// <i> Indicates whether the external interrupt 3 filter is enabled or not
// <id> eic_arch_filten3
#ifndef CONF_EIC_FILTEN3
#define CONF_EIC_FILTEN3 0
#endif
// <q> External Interrupt 3 Event Output Enable
// <i> Indicates whether the external interrupt 3 event output is enabled or not
// <id> eic_arch_extinteo3
#ifndef CONF_EIC_EXTINTEO3
#define CONF_EIC_EXTINTEO3 0
#endif
// <y> Input 3 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense3
#ifndef CONF_EIC_SENSE3
#define CONF_EIC_SENSE3 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 3 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 3 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch3
#ifndef CONF_EIC_ASYNCH3
#define CONF_EIC_ASYNCH3 0
#endif
// </e>
// <e> Interrupt 4 Settings
// <id> eic_arch_enable_irq_setting4
#ifndef CONF_EIC_ENABLE_IRQ_SETTING4
#define CONF_EIC_ENABLE_IRQ_SETTING4 0
#endif
// <q> External Interrupt 4 Filter Enable
// <i> Indicates whether the external interrupt 4 filter is enabled or not
// <id> eic_arch_filten4
#ifndef CONF_EIC_FILTEN4
#define CONF_EIC_FILTEN4 0
#endif
// <q> External Interrupt 4 Event Output Enable
// <i> Indicates whether the external interrupt 4 event output is enabled or not
// <id> eic_arch_extinteo4
#ifndef CONF_EIC_EXTINTEO4
#define CONF_EIC_EXTINTEO4 0
#endif
// <y> Input 4 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense4
#ifndef CONF_EIC_SENSE4
#define CONF_EIC_SENSE4 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 4 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 4 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch4
#ifndef CONF_EIC_ASYNCH4
#define CONF_EIC_ASYNCH4 0
#endif
// </e>
// <e> Interrupt 5 Settings
// <id> eic_arch_enable_irq_setting5
#ifndef CONF_EIC_ENABLE_IRQ_SETTING5
#define CONF_EIC_ENABLE_IRQ_SETTING5 1
#endif
// <q> External Interrupt 5 Filter Enable
// <i> Indicates whether the external interrupt 5 filter is enabled or not
// <id> eic_arch_filten5
#ifndef CONF_EIC_FILTEN5
#define CONF_EIC_FILTEN5 0
#endif
// <q> External Interrupt 5 Event Output Enable
// <i> Indicates whether the external interrupt 5 event output is enabled or not
// <id> eic_arch_extinteo5
#ifndef CONF_EIC_EXTINTEO5
#define CONF_EIC_EXTINTEO5 0
#endif
// <y> Input 5 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense5
#ifndef CONF_EIC_SENSE5
#define CONF_EIC_SENSE5 EIC_NMICTRL_NMISENSE_RISE_Val
#endif
// <q> External Interrupt 5 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 5 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch5
#ifndef CONF_EIC_ASYNCH5
#define CONF_EIC_ASYNCH5 0
#endif
// </e>
// <e> Interrupt 6 Settings
// <id> eic_arch_enable_irq_setting6
#ifndef CONF_EIC_ENABLE_IRQ_SETTING6
#define CONF_EIC_ENABLE_IRQ_SETTING6 1
#endif
// <q> External Interrupt 6 Filter Enable
// <i> Indicates whether the external interrupt 6 filter is enabled or not
// <id> eic_arch_filten6
#ifndef CONF_EIC_FILTEN6
#define CONF_EIC_FILTEN6 0
#endif
// <q> External Interrupt 6 Event Output Enable
// <i> Indicates whether the external interrupt 6 event output is enabled or not
// <id> eic_arch_extinteo6
#ifndef CONF_EIC_EXTINTEO6
#define CONF_EIC_EXTINTEO6 0
#endif
// <y> Input 6 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense6
#ifndef CONF_EIC_SENSE6
#define CONF_EIC_SENSE6 EIC_NMICTRL_NMISENSE_RISE_Val
#endif
// <q> External Interrupt 6 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 6 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch6
#ifndef CONF_EIC_ASYNCH6
#define CONF_EIC_ASYNCH6 0
#endif
// </e>
// <e> Interrupt 7 Settings
// <id> eic_arch_enable_irq_setting7
#ifndef CONF_EIC_ENABLE_IRQ_SETTING7
#define CONF_EIC_ENABLE_IRQ_SETTING7 1
#endif
// <q> External Interrupt 7 Filter Enable
// <i> Indicates whether the external interrupt 7 filter is enabled or not
// <id> eic_arch_filten7
#ifndef CONF_EIC_FILTEN7
#define CONF_EIC_FILTEN7 0
#endif
// <q> External Interrupt 7 Event Output Enable
// <i> Indicates whether the external interrupt 7 event output is enabled or not
// <id> eic_arch_extinteo7
#ifndef CONF_EIC_EXTINTEO7
#define CONF_EIC_EXTINTEO7 0
#endif
// <y> Input 7 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense7
#ifndef CONF_EIC_SENSE7
#define CONF_EIC_SENSE7 EIC_NMICTRL_NMISENSE_RISE_Val
#endif
// <q> External Interrupt 7 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 7 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch7
#ifndef CONF_EIC_ASYNCH7
#define CONF_EIC_ASYNCH7 0
#endif
// </e>
// <e> Interrupt 8 Settings
// <id> eic_arch_enable_irq_setting8
#ifndef CONF_EIC_ENABLE_IRQ_SETTING8
#define CONF_EIC_ENABLE_IRQ_SETTING8 0
#endif
// <q> External Interrupt 8 Filter Enable
// <i> Indicates whether the external interrupt 8 filter is enabled or not
// <id> eic_arch_filten8
#ifndef CONF_EIC_FILTEN8
#define CONF_EIC_FILTEN8 0
#endif
// <q> External Interrupt 8 Event Output Enable
// <i> Indicates whether the external interrupt 8 event output is enabled or not
// <id> eic_arch_extinteo8
#ifndef CONF_EIC_EXTINTEO8
#define CONF_EIC_EXTINTEO8 0
#endif
// <y> Input 8 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense8
#ifndef CONF_EIC_SENSE8
#define CONF_EIC_SENSE8 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 8 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 8 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch8
#ifndef CONF_EIC_ASYNCH8
#define CONF_EIC_ASYNCH8 0
#endif
// </e>
// <e> Interrupt 9 Settings
// <id> eic_arch_enable_irq_setting9
#ifndef CONF_EIC_ENABLE_IRQ_SETTING9
#define CONF_EIC_ENABLE_IRQ_SETTING9 0
#endif
// <q> External Interrupt 9 Filter Enable
// <i> Indicates whether the external interrupt 9 filter is enabled or not
// <id> eic_arch_filten9
#ifndef CONF_EIC_FILTEN9
#define CONF_EIC_FILTEN9 0
#endif
// <q> External Interrupt 9 Event Output Enable
// <i> Indicates whether the external interrupt 9 event output is enabled or not
// <id> eic_arch_extinteo9
#ifndef CONF_EIC_EXTINTEO9
#define CONF_EIC_EXTINTEO9 0
#endif
// <y> Input 9 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense9
#ifndef CONF_EIC_SENSE9
#define CONF_EIC_SENSE9 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 9 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 9 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch9
#ifndef CONF_EIC_ASYNCH9
#define CONF_EIC_ASYNCH9 0
#endif
// </e>
// <e> Interrupt 10 Settings
// <id> eic_arch_enable_irq_setting10
#ifndef CONF_EIC_ENABLE_IRQ_SETTING10
#define CONF_EIC_ENABLE_IRQ_SETTING10 0
#endif
// <q> External Interrupt 10 Filter Enable
// <i> Indicates whether the external interrupt 10 filter is enabled or not
// <id> eic_arch_filten10
#ifndef CONF_EIC_FILTEN10
#define CONF_EIC_FILTEN10 0
#endif
// <q> External Interrupt 10 Event Output Enable
// <i> Indicates whether the external interrupt 10 event output is enabled or not
// <id> eic_arch_extinteo10
#ifndef CONF_EIC_EXTINTEO10
#define CONF_EIC_EXTINTEO10 0
#endif
// <y> Input 10 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense10
#ifndef CONF_EIC_SENSE10
#define CONF_EIC_SENSE10 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 10 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 10 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch10
#ifndef CONF_EIC_ASYNCH10
#define CONF_EIC_ASYNCH10 0
#endif
// </e>
// <e> Interrupt 11 Settings
// <id> eic_arch_enable_irq_setting11
#ifndef CONF_EIC_ENABLE_IRQ_SETTING11
#define CONF_EIC_ENABLE_IRQ_SETTING11 0
#endif
// <q> External Interrupt 11 Filter Enable
// <i> Indicates whether the external interrupt 11 filter is enabled or not
// <id> eic_arch_filten11
#ifndef CONF_EIC_FILTEN11
#define CONF_EIC_FILTEN11 0
#endif
// <q> External Interrupt 11 Event Output Enable
// <i> Indicates whether the external interrupt 11 event output is enabled or not
// <id> eic_arch_extinteo11
#ifndef CONF_EIC_EXTINTEO11
#define CONF_EIC_EXTINTEO11 0
#endif
// <y> Input 11 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense11
#ifndef CONF_EIC_SENSE11
#define CONF_EIC_SENSE11 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 11 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 11 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch11
#ifndef CONF_EIC_ASYNCH11
#define CONF_EIC_ASYNCH11 0
#endif
// </e>
// <e> Interrupt 12 Settings
// <id> eic_arch_enable_irq_setting12
#ifndef CONF_EIC_ENABLE_IRQ_SETTING12
#define CONF_EIC_ENABLE_IRQ_SETTING12 0
#endif
// <q> External Interrupt 12 Filter Enable
// <i> Indicates whether the external interrupt 12 filter is enabled or not
// <id> eic_arch_filten12
#ifndef CONF_EIC_FILTEN12
#define CONF_EIC_FILTEN12 0
#endif
// <q> External Interrupt 12 Event Output Enable
// <i> Indicates whether the external interrupt 12 event output is enabled or not
// <id> eic_arch_extinteo12
#ifndef CONF_EIC_EXTINTEO12
#define CONF_EIC_EXTINTEO12 0
#endif
// <y> Input 12 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense12
#ifndef CONF_EIC_SENSE12
#define CONF_EIC_SENSE12 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 12 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 12 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch12
#ifndef CONF_EIC_ASYNCH12
#define CONF_EIC_ASYNCH12 0
#endif
// </e>
// <e> Interrupt 13 Settings
// <id> eic_arch_enable_irq_setting13
#ifndef CONF_EIC_ENABLE_IRQ_SETTING13
#define CONF_EIC_ENABLE_IRQ_SETTING13 0
#endif
// <q> External Interrupt 13 Filter Enable
// <i> Indicates whether the external interrupt 13 filter is enabled or not
// <id> eic_arch_filten13
#ifndef CONF_EIC_FILTEN13
#define CONF_EIC_FILTEN13 0
#endif
// <q> External Interrupt 13 Event Output Enable
// <i> Indicates whether the external interrupt 13 event output is enabled or not
// <id> eic_arch_extinteo13
#ifndef CONF_EIC_EXTINTEO13
#define CONF_EIC_EXTINTEO13 0
#endif
// <y> Input 13 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense13
#ifndef CONF_EIC_SENSE13
#define CONF_EIC_SENSE13 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 13 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 13 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch13
#ifndef CONF_EIC_ASYNCH13
#define CONF_EIC_ASYNCH13 0
#endif
// </e>
// <e> Interrupt 14 Settings
// <id> eic_arch_enable_irq_setting14
#ifndef CONF_EIC_ENABLE_IRQ_SETTING14
#define CONF_EIC_ENABLE_IRQ_SETTING14 0
#endif
// <q> External Interrupt 14 Filter Enable
// <i> Indicates whether the external interrupt 14 filter is enabled or not
// <id> eic_arch_filten14
#ifndef CONF_EIC_FILTEN14
#define CONF_EIC_FILTEN14 0
#endif
// <q> External Interrupt 14 Event Output Enable
// <i> Indicates whether the external interrupt 14 event output is enabled or not
// <id> eic_arch_extinteo14
#ifndef CONF_EIC_EXTINTEO14
#define CONF_EIC_EXTINTEO14 0
#endif
// <y> Input 14 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense14
#ifndef CONF_EIC_SENSE14
#define CONF_EIC_SENSE14 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 14 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 14 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch14
#ifndef CONF_EIC_ASYNCH14
#define CONF_EIC_ASYNCH14 0
#endif
// </e>
// <e> Interrupt 15 Settings
// <id> eic_arch_enable_irq_setting15
#ifndef CONF_EIC_ENABLE_IRQ_SETTING15
#define CONF_EIC_ENABLE_IRQ_SETTING15 0
#endif
// <q> External Interrupt 15 Filter Enable
// <i> Indicates whether the external interrupt 15 filter is enabled or not
// <id> eic_arch_filten15
#ifndef CONF_EIC_FILTEN15
#define CONF_EIC_FILTEN15 0
#endif
// <q> External Interrupt 15 Event Output Enable
// <i> Indicates whether the external interrupt 15 event output is enabled or not
// <id> eic_arch_extinteo15
#ifndef CONF_EIC_EXTINTEO15
#define CONF_EIC_EXTINTEO15 0
#endif
// <y> Input 15 Sense Configuration
// <EIC_NMICTRL_NMISENSE_NONE_Val"> No detection
// <EIC_NMICTRL_NMISENSE_RISE_Val"> Rising-edge detection
// <EIC_NMICTRL_NMISENSE_FALL_Val"> Falling-edge detection
// <EIC_NMICTRL_NMISENSE_BOTH_Val"> Both-edges detection
// <EIC_NMICTRL_NMISENSE_HIGH_Val"> High-level detection
// <EIC_NMICTRL_NMISENSE_LOW_Val"> Low-level detection
// <i> This defines input sense trigger
// <id> eic_arch_sense15
#ifndef CONF_EIC_SENSE15
#define CONF_EIC_SENSE15 EIC_NMICTRL_NMISENSE_NONE_Val
#endif
// <q> External Interrupt 15 Asynchronous Edge Detection Mode
// <i> Indicates the external interrupt 15 detection mode operated synchronously or asynchronousl
// <id> eic_arch_asynch15
#ifndef CONF_EIC_ASYNCH15
#define CONF_EIC_ASYNCH15 0
#endif
// </e>
#define CONFIG_EIC_EXTINT_MAP {5, PIN_PB05}, {6, PIN_PA22}, {7, PIN_PA23},
// <<< end of configuration section >>>
#endif // HPL_EIC_CONFIG_H

383
Smol Watch Project/My Project/Config/hpl_gclk_config.h
View file

@ -1,383 +0,0 @@
/* Auto-generated config file hpl_gclk_config.h */
#ifndef HPL_GCLK_CONFIG_H
#define HPL_GCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> Generic clock generator 0 configuration
// <i> Indicates whether generic clock 0 configuration is enabled or not
// <id> enable_gclk_gen_0
#ifndef CONF_GCLK_GENERATOR_0_CONFIG
#define CONF_GCLK_GENERATOR_0_CONFIG 1
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 0 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 0
// <id> gclk_gen_0_oscillator
#ifndef CONF_GCLK_GEN_0_SOURCE
#define CONF_GCLK_GEN_0_SOURCE GCLK_GENCTRL_SRC_OSC16M
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_0_runstdby
#ifndef CONF_GCLK_GEN_0_RUNSTDBY
#define CONF_GCLK_GEN_0_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_0_div_sel
#ifndef CONF_GCLK_GEN_0_DIVSEL
#define CONF_GCLK_GEN_0_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_0_oe
#ifndef CONF_GCLK_GEN_0_OE
#define CONF_GCLK_GEN_0_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_0_oov
#ifndef CONF_GCLK_GEN_0_OOV
#define CONF_GCLK_GEN_0_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_0_idc
#ifndef CONF_GCLK_GEN_0_IDC
#define CONF_GCLK_GEN_0_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_0_enable
#ifndef CONF_GCLK_GEN_0_GENEN
#define CONF_GCLK_GEN_0_GENEN 1
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 0 division <0x0000-0xFFFF>
// <id> gclk_gen_0_div
#ifndef CONF_GCLK_GEN_0_DIV
#define CONF_GCLK_GEN_0_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 1 configuration
// <i> Indicates whether generic clock 1 configuration is enabled or not
// <id> enable_gclk_gen_1
#ifndef CONF_GCLK_GENERATOR_1_CONFIG
#define CONF_GCLK_GENERATOR_1_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 1 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 1
// <id> gclk_gen_1_oscillator
#ifndef CONF_GCLK_GEN_1_SOURCE
#define CONF_GCLK_GEN_1_SOURCE GCLK_GENCTRL_SRC_XOSC
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_1_runstdby
#ifndef CONF_GCLK_GEN_1_RUNSTDBY
#define CONF_GCLK_GEN_1_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_1_div_sel
#ifndef CONF_GCLK_GEN_1_DIVSEL
#define CONF_GCLK_GEN_1_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_1_oe
#ifndef CONF_GCLK_GEN_1_OE
#define CONF_GCLK_GEN_1_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_1_oov
#ifndef CONF_GCLK_GEN_1_OOV
#define CONF_GCLK_GEN_1_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_1_idc
#ifndef CONF_GCLK_GEN_1_IDC
#define CONF_GCLK_GEN_1_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_1_enable
#ifndef CONF_GCLK_GEN_1_GENEN
#define CONF_GCLK_GEN_1_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 1 division <0x0000-0xFFFF>
// <id> gclk_gen_1_div
#ifndef CONF_GCLK_GEN_1_DIV
#define CONF_GCLK_GEN_1_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 2 configuration
// <i> Indicates whether generic clock 2 configuration is enabled or not
// <id> enable_gclk_gen_2
#ifndef CONF_GCLK_GENERATOR_2_CONFIG
#define CONF_GCLK_GENERATOR_2_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 2 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 2
// <id> gclk_gen_2_oscillator
#ifndef CONF_GCLK_GEN_2_SOURCE
#define CONF_GCLK_GEN_2_SOURCE GCLK_GENCTRL_SRC_XOSC
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_2_runstdby
#ifndef CONF_GCLK_GEN_2_RUNSTDBY
#define CONF_GCLK_GEN_2_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_2_div_sel
#ifndef CONF_GCLK_GEN_2_DIVSEL
#define CONF_GCLK_GEN_2_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_2_oe
#ifndef CONF_GCLK_GEN_2_OE
#define CONF_GCLK_GEN_2_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_2_oov
#ifndef CONF_GCLK_GEN_2_OOV
#define CONF_GCLK_GEN_2_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_2_idc
#ifndef CONF_GCLK_GEN_2_IDC
#define CONF_GCLK_GEN_2_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_2_enable
#ifndef CONF_GCLK_GEN_2_GENEN
#define CONF_GCLK_GEN_2_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 2 division <0x0000-0xFFFF>
// <id> gclk_gen_2_div
#ifndef CONF_GCLK_GEN_2_DIV
#define CONF_GCLK_GEN_2_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 3 configuration
// <i> Indicates whether generic clock 3 configuration is enabled or not
// <id> enable_gclk_gen_3
#ifndef CONF_GCLK_GENERATOR_3_CONFIG
#define CONF_GCLK_GENERATOR_3_CONFIG 1
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 3 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 3
// <id> gclk_gen_3_oscillator
#ifndef CONF_GCLK_GEN_3_SOURCE
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_3_runstdby
#ifndef CONF_GCLK_GEN_3_RUNSTDBY
#define CONF_GCLK_GEN_3_RUNSTDBY 1
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_3_div_sel
#ifndef CONF_GCLK_GEN_3_DIVSEL
#define CONF_GCLK_GEN_3_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_3_oe
#ifndef CONF_GCLK_GEN_3_OE
#define CONF_GCLK_GEN_3_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_3_oov
#ifndef CONF_GCLK_GEN_3_OOV
#define CONF_GCLK_GEN_3_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_3_idc
#ifndef CONF_GCLK_GEN_3_IDC
#define CONF_GCLK_GEN_3_IDC 1
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_3_enable
#ifndef CONF_GCLK_GEN_3_GENEN
#define CONF_GCLK_GEN_3_GENEN 1
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 3 division <0x0000-0xFFFF>
// <id> gclk_gen_3_div
#ifndef CONF_GCLK_GEN_3_DIV
#define CONF_GCLK_GEN_3_DIV 1
#endif
// </h>
// </e>
// <e> Generic clock generator 4 configuration
// <i> Indicates whether generic clock 4 configuration is enabled or not
// <id> enable_gclk_gen_4
#ifndef CONF_GCLK_GENERATOR_4_CONFIG
#define CONF_GCLK_GENERATOR_4_CONFIG 0
#endif
// <h> Generic Clock Generator Control
// <y> Generic clock generator 4 source
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_GENCTRL_SRC_GCLKIN"> Generic clock generator input pad
// <GCLK_GENCTRL_SRC_GCLKGEN1"> Generic clock generator 1
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_OSC16M"> 16MHz Internal Oscillator (OSC16M)
// <GCLK_GENCTRL_SRC_DFLL48M"> Digital Frequency Locked Loop (DFLL48M)
// <GCLK_GENCTRL_SRC_DPLL96M"> Fractional Digital Phase Locked Loop (FDPLL96M)
// <i> This defines the clock source for generic clock generator 4
// <id> gclk_gen_4_oscillator
#ifndef CONF_GCLK_GEN_4_SOURCE
#define CONF_GCLK_GEN_4_SOURCE GCLK_GENCTRL_SRC_XOSC
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_4_runstdby
#ifndef CONF_GCLK_GEN_4_RUNSTDBY
#define CONF_GCLK_GEN_4_RUNSTDBY 0
#endif
// <q> Divide Selection
// <i> Indicates whether Divide Selection is enabled or not
//<id> gclk_gen_4_div_sel
#ifndef CONF_GCLK_GEN_4_DIVSEL
#define CONF_GCLK_GEN_4_DIVSEL 0
#endif
// <q> Output Enable
// <i> Indicates whether Output Enable is enabled or not
// <id> gclk_arch_gen_4_oe
#ifndef CONF_GCLK_GEN_4_OE
#define CONF_GCLK_GEN_4_OE 0
#endif
// <q> Output Off Value
// <i> Indicates whether Output Off Value is enabled or not
// <id> gclk_arch_gen_4_oov
#ifndef CONF_GCLK_GEN_4_OOV
#define CONF_GCLK_GEN_4_OOV 0
#endif
// <q> Improve Duty Cycle
// <i> Indicates whether Improve Duty Cycle is enabled or not
// <id> gclk_arch_gen_4_idc
#ifndef CONF_GCLK_GEN_4_IDC
#define CONF_GCLK_GEN_4_IDC 0
#endif
// <q> Generic Clock Generator Enable
// <i> Indicates whether Generic Clock Generator Enable is enabled or not
// <id> gclk_arch_gen_4_enable
#ifndef CONF_GCLK_GEN_4_GENEN
#define CONF_GCLK_GEN_4_GENEN 0
#endif
// </h>
//<h> Generic Clock Generator Division
//<o> Generic clock generator 4 division <0x0000-0xFFFF>
// <id> gclk_gen_4_div
#ifndef CONF_GCLK_GEN_4_DIV
#define CONF_GCLK_GEN_4_DIV 1
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_GCLK_CONFIG_H

85
Smol Watch Project/My Project/Config/hpl_mclk_config.h
View file

@ -1,85 +0,0 @@
/* Auto-generated config file hpl_mclk_config.h */
#ifndef HPL_MCLK_CONFIG_H
#define HPL_MCLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
// <e> System Configuration
// <i> Indicates whether configuration for system is enabled or not
// <id> enable_cpu_clock
#ifndef CONF_SYSTEM_CONFIG
#define CONF_SYSTEM_CONFIG 1
#endif
// <h> Basic settings
// <y> CPU Clock source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <i> This defines the clock source for the CPU
// <id> cpu_clock_source
#ifndef CONF_CPU_SRC
#define CONF_CPU_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> CPU Clock Division Factor
// <MCLK_CPUDIV_CPUDIV_DIV1_Val"> 1
// <MCLK_CPUDIV_CPUDIV_DIV2_Val"> 2
// <MCLK_CPUDIV_CPUDIV_DIV4_Val"> 4
// <MCLK_CPUDIV_CPUDIV_DIV8_Val"> 8
// <MCLK_CPUDIV_CPUDIV_DIV16_Val"> 16
// <MCLK_CPUDIV_CPUDIV_DIV32_Val"> 32
// <MCLK_CPUDIV_CPUDIV_DIV64_Val"> 64
// <MCLK_CPUDIV_CPUDIV_DIV128_Val"> 128
// <i> Prescalar for CPU clock
// <id> cpu_div
#ifndef CONF_MCLK_CPUDIV
#define CONF_MCLK_CPUDIV MCLK_CPUDIV_CPUDIV_DIV1_Val
#endif
// <y> Backup Clock Division
// <MCLK_BUPDIV_BUPDIV_DIV1_Val"> Divide by 1
// <MCLK_BUPDIV_BUPDIV_DIV2_Val"> Divide by 2
// <MCLK_BUPDIV_BUPDIV_DIV4_Val"> Divide by 4
// <MCLK_BUPDIV_BUPDIV_DIV8_Val"> Divide by 8
// <MCLK_BUPDIV_BUPDIV_DIV16_Val"> Divide by 16
// <MCLK_BUPDIV_BUPDIV_DIV32_Val"> Divide by 32
// <MCLK_BUPDIV_BUPDIV_DIV64_Val"> Divide by 64
// <MCLK_BUPDIV_BUPDIV_DIV128_Val"> Divide by 128
// <id> mclk_arch_bupdiv
#ifndef CONF_MCLK_BUPDIV
#define CONF_MCLK_BUPDIV MCLK_BUPDIV_BUPDIV_DIV1_Val
#endif
// </h>
// <h> NVM Settings
// <o> NVM Wait States
// <i> These bits select the number of wait states for a read operation.
// <0=> 0
// <1=> 1
// <2=> 2
// <3=> 3
// <4=> 4
// <5=> 5
// <6=> 6
// <7=> 7
// <8=> 8
// <9=> 9
// <10=> 10
// <11=> 11
// <12=> 12
// <13=> 13
// <14=> 14
// <15=> 15
// <id> nvm_wait_states
#ifndef CONF_NVM_WAIT_STATE
#define CONF_NVM_WAIT_STATE 0
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_MCLK_CONFIG_H

173
Smol Watch Project/My Project/Config/hpl_osc32kctrl_config.h
View file

@ -1,173 +0,0 @@
/* Auto-generated config file hpl_osc32kctrl_config.h */
#ifndef HPL_OSC32KCTRL_CONFIG_H
#define HPL_OSC32KCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> RTC Source configuration
// <id> enable_rtc_source
#ifndef CONF_RTCCTRL_CONFIG
#define CONF_RTCCTRL_CONFIG 0
#endif
// <h> RTC source control
// <y> RTC Clock Source Selection
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <i> This defines the clock source for RTC
// <id> rtc_source_oscillator
#ifndef CONF_RTCCTRL_SRC
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K
#endif
// <q> Use 1 kHz output
// <id> rtc_1khz_selection
#ifndef CONF_RTCCTRL_1KHZ
#define CONF_RTCCTRL_1KHZ 1
#endif
#if CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_OSCULP32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_ULP1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_ULP32K_Val)
#elif CONF_RTCCTRL_SRC == GCLK_GENCTRL_SRC_XOSC32K
#define CONF_RTCCTRL (CONF_RTCCTRL_1KHZ ? OSC32KCTRL_RTCCTRL_RTCSEL_XOSC1K_Val : OSC32KCTRL_RTCCTRL_RTCSEL_XOSC32K_Val)
#else
#error unexpected CONF_RTCCTRL_SRC
#endif
// </h>
// </e>
// <e> SLCD Source configuration
// <id> enable_slcd_source
#ifndef CONF_SLCDCTRL_CONFIG
#define CONF_SLCDCTRL_CONFIG 0
#endif
// <h> SLCD source control
// <y> SLCD Clock Source Selection
// <GCLK_GENCTRL_SRC_OSCULP32K"> 32kHz Ultra Low Power Internal Oscillator (OSCULP32K)
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <i> This defines the clock source for SLCD
// <id> slcd_source_oscillator
#ifndef CONF_SLCDCTRL_SRC
#define CONF_SLCDCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K
#endif
// </h>
// </e>
// <e> 32kHz External Crystal Oscillator Configuration
// <i> Indicates whether configuration for External 32K Osc is enabled or not
// <id> enable_xosc32k
#ifndef CONF_XOSC32K_CONFIG
#define CONF_XOSC32K_CONFIG 1
#endif
// <h> 32kHz External Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether 32kHz External Crystal Oscillator is enabled or not
// <id> xosc32k_arch_enable
#ifndef CONF_XOSC32K_ENABLE
#define CONF_XOSC32K_ENABLE 1
#endif
// <o> Start-Up Time
// <0x0=>62592us
// <0x1=>125092us
// <0x2=>500092us
// <0x3=>1000092us
// <0x4=>2000092us
// <0x5=>4000092us
// <0x6=>8000092us
// <id> xosc32k_arch_startup
#ifndef CONF_XOSC32K_STARTUP
#define CONF_XOSC32K_STARTUP 0x3
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc32k_arch_ondemand
#ifndef CONF_XOSC32K_ONDEMAND
#define CONF_XOSC32K_ONDEMAND 0
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc32k_arch_runstdby
#ifndef CONF_XOSC32K_RUNSTDBY
#define CONF_XOSC32K_RUNSTDBY 1
#endif
// <q> 1kHz Output Enable
// <i> Indicates whether 1kHz Output is enabled or not
// <id> xosc32k_arch_en1k
#ifndef CONF_XOSC32K_EN1K
#define CONF_XOSC32K_EN1K 1
#endif
// <q> 32kHz Output Enable
// <i> Indicates whether 32kHz Output is enabled or not
// <id> xosc32k_arch_en32k
#ifndef CONF_XOSC32K_EN32K
#define CONF_XOSC32K_EN32K 1
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc32k_arch_swben
#ifndef CONF_XOSC32K_SWBEN
#define CONF_XOSC32K_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc32k_arch_cfden
#ifndef CONF_XOSC32K_CFDEN
#define CONF_XOSC32K_CFDEN 0
#endif
// <q> Clock Failure Detector Event Out
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
// <id> xosc32k_arch_cfdeo
#ifndef CONF_XOSC32K_CFDEO
#define CONF_XOSC32K_CFDEO 0
#endif
// <q> Crystal connected to XIN32/XOUT32 Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc32k_arch_xtalen
#ifndef CONF_XOSC32K_XTALEN
#define CONF_XOSC32K_XTALEN 1
#endif
// </h>
// </e>
// <e> 32kHz Ultra Low Power Internal Oscillator Configuration
// <i> Indicates whether configuration for OSCULP32K is enabled or not
// <id> enable_osculp32k
#ifndef CONF_OSCULP32K_CONFIG
#define CONF_OSCULP32K_CONFIG 1
#endif
// <h> 32kHz Ultra Low Power Internal Oscillator Control
// <q> Oscillator Calibration Control
// <i> Indicates whether Oscillator Calibration is enabled or not
// <id> osculp32k_calib_enable
#ifndef CONF_OSCULP32K_CALIB_ENABLE
#define CONF_OSCULP32K_CALIB_ENABLE 0
#endif
// <o> Oscillator Calibration <0x0-0x1F>
// <id> osculp32k_calib
#ifndef CONF_OSCULP32K_CALIB
#define CONF_OSCULP32K_CALIB 0x0
#endif
// </h>
// </e>
// <<< end of configuration section >>>
#endif // HPL_OSC32KCTRL_CONFIG_H

483
Smol Watch Project/My Project/Config/hpl_oscctrl_config.h
View file

@ -1,483 +0,0 @@
/* Auto-generated config file hpl_oscctrl_config.h */
#ifndef HPL_OSCCTRL_CONFIG_H
#define HPL_OSCCTRL_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> External Multipurpose Crystal Oscillator Configuration
// <i> Indicates whether configuration for XOSC is enabled or not
// <id> enable_xosc
#ifndef CONF_XOSC_CONFIG
#define CONF_XOSC_CONFIG 0
#endif
// <o> Frequency <400000-32000000>
// <i> Oscillation frequency of the resonator connected to the External Multipurpose Crystal Oscillator.
// <id> xosc_frequency
#ifndef CONF_XOSC_FREQUENCY
#define CONF_XOSC_FREQUENCY 400000
#endif
// <h> External Multipurpose Crystal Oscillator Control
// <q> Oscillator enable
// <i> Indicates whether External Multipurpose Crystal Oscillator is enabled or not
// <id> xosc_arch_enable
#ifndef CONF_XOSC_ENABLE
#define CONF_XOSC_ENABLE 0
#endif
// <o> Start-Up Time
// <0x0=>31us
// <0x1=>61us
// <0x2=>122us
// <0x3=>244us
// <0x4=>488us
// <0x5=>977us
// <0x6=>1953us
// <0x7=>3906us
// <0x8=>7813us
// <0x9=>15625us
// <0xA=>31250us
// <0xB=>62500us
// <0xC=>125000us
// <0xD=>250000us
// <0xE=>500000us
// <0xF=>1000000us
// <id> xosc_arch_startup
#ifndef CONF_XOSC_STARTUP
#define CONF_XOSC_STARTUP 0x0
#endif
// <q> Automatic Amplitude Gain Control
// <i> Indicates whether Automatic Amplitude Gain Control is enabled or not
// <id> xosc_arch_ampgc
#ifndef CONF_XOSC_AMPGC
#define CONF_XOSC_AMPGC 0
#endif
// <o> External Multipurpose Crystal Oscillator Gain
// <0x0=>2MHz
// <0x1=>4MHz
// <0x2=>8MHz
// <0x3=>16MHz
// <0x4=>30MHz
// <id> xosc_arch_gain
#ifndef CONF_XOSC_GAIN
#define CONF_XOSC_GAIN 0x0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> xosc_arch_ondemand
#ifndef CONF_XOSC_ONDEMAND
#define CONF_XOSC_ONDEMAND 1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> xosc_arch_runstdby
#ifndef CONF_XOSC_RUNSTDBY
#define CONF_XOSC_RUNSTDBY 0
#endif
// <q> Clock Switch Back
// <i> Indicates whether Clock Switch Back is enabled or not
// <id> xosc_arch_swben
#ifndef CONF_XOSC_SWBEN
#define CONF_XOSC_SWBEN 0
#endif
// <q> Clock Failure Detector
// <i> Indicates whether Clock Failure Detector is enabled or not
// <id> xosc_arch_cfden
#ifndef CONF_XOSC_CFDEN
#define CONF_XOSC_CFDEN 0
#endif
// <q> Clock Failure Detector Event Out
// <i> Indicates whether Clock Failure Detector Event Out is enabled or not
// <id> xosc_arch_cfdeo
#ifndef CONF_XOSC_CFDEO
#define CONF_XOSC_CFDEO 0
#endif
// <q> Crystal connected to XIN/XOUT Enable
// <i> Indicates whether the connections between the I/O pads and the external clock or crystal oscillator is enabled or not
// <id> xosc_arch_xtalen
#ifndef CONF_XOSC_XTALEN
#define CONF_XOSC_XTALEN 0
#endif
//</h>
//</e>
// <e> 16MHz Internal Oscillator Configuration
// <i> Indicates whether configuration for OSC8M is enabled or not
// <id> enable_osc16m
#ifndef CONF_OSC16M_CONFIG
#define CONF_OSC16M_CONFIG 1
#endif
// <h> 16MHz Internal Oscillator Control
// <q> Enable
// <i> Indicates whether 16MHz Internal Oscillator is enabled or not
// <id> osc16m_arch_enable
#ifndef CONF_OSC16M_ENABLE
#define CONF_OSC16M_ENABLE 1
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> osc16m_arch_ondemand
#ifndef CONF_OSC16M_ONDEMAND
#define CONF_OSC16M_ONDEMAND 1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> osc16m_arch_runstdby
#ifndef CONF_OSC16M_RUNSTDBY
#define CONF_OSC16M_RUNSTDBY 0
#endif
// <y> Oscillator Frequency Selection(Mhz)
// <OSCCTRL_OSC16MCTRL_FSEL_4_Val"> 4
// <OSCCTRL_OSC16MCTRL_FSEL_8_Val"> 8
// <OSCCTRL_OSC16MCTRL_FSEL_12_Val"> 12
// <OSCCTRL_OSC16MCTRL_FSEL_16_Val"> 16
// <i> This defines the oscillator frequency (Mhz)
// <id> osc16m_freq
#ifndef CONF_OSC16M_FSEL
#define CONF_OSC16M_FSEL OSCCTRL_OSC16MCTRL_FSEL_4_Val
#endif
// <q> Oscillator Calibration Control
// <i> Indicates whether Oscillator Calibration is enabled or not
// <id> osc16m_arch_calib_enable
#ifndef CONF_OSC16M_CALIB_ENABLE
#define CONF_OSC16M_CALIB_ENABLE 0
#endif
// <o> 4MHz Frequency Calibration <0x0-0x3F>
// <id> osc16m_arch_4m_fcal
#ifndef CONF_OSC16M_FCAL
#define CONF_OSC16M_4M_FCAL 0
#endif
// <o> 4MHz Temperature Calibration <0x0-0x3F>
// <id> osc16m_arch_4m_tcal
#ifndef CONF_OSC16M_TCAL
#define CONF_OSC16M_4M_TCAL 0
#endif
// <o> 8MHz Frequency Calibration <0x0-0x3F>
// <id> osc16m_arch_8m_fcal
#ifndef CONF_OSC16M_FCAL
#define CONF_OSC16M_8M_FCAL 0
#endif
// <o> 8MHz Temperature Calibration <0x0-0x3F>
// <id> osc16m_arch_8m_tcal
#ifndef CONF_OSC16M_TCAL
#define CONF_OSC16M_8M_TCAL 0
#endif
// <o> 12MHz Frequency Calibration <0x0-0x3F>
// <id> osc16m_arch_12m_fcal
#ifndef CONF_OSC16M_FCAL
#define CONF_OSC16M_12M_FCAL 0
#endif
// <o> 12MHz Temperature Calibration <0x0-0x3F>
// <id> osc16m_arch_12m_tcal
#ifndef CONF_OSC16M_TCAL
#define CONF_OSC16M_12M_TCAL 0
#endif
// <o> 16MHz Frequency Calibration <0x0-0x3F>
// <id> osc16m_arch_fcal
#ifndef CONF_OSC16M_FCAL
#define CONF_OSC16M_16M_FCAL 0
#endif
// <o> 16MHz Temperature Calibration <0x0-0x3F>
// <id> osc16m_arch_16m_tcal
#ifndef CONF_OSC16M_TCAL
#define CONF_OSC16M_16M_TCAL 0
#endif
//</h>
//</e>
// <e> DFLL Configuration
// <i> Indicates whether configuration for DFLL is enabled or not
// <id> enable_dfll48m
#ifndef CONF_DFLL_CONFIG
#define CONF_DFLL_CONFIG 0
#endif
// <y> Reference Clock Source
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the clock source.
// <id> dfll48m_ref_clock
#ifndef CONF_DFLL_GCLK
#define CONF_DFLL_GCLK GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
// <h> Digital Frequency Locked Loop Control
// <q> DFLL Enable
// <i> Indicates whether DFLL is enabled or not
// <id> dfll48m_arch_enable
#ifndef CONF_DFLL_ENABLE
#define CONF_DFLL_ENABLE 0
#endif
// <q> Wait Lock
// <i> Indicates whether Wait Lock is enabled or not
// <id> dfll_arch_waitlock
#ifndef CONF_DFLL_WAITLOCK
#define CONF_DFLL_WAITLOCK 0
#endif
// <q> Bypass Coarse Lock
// <i> Indicates whether Bypass Coarse Lock is enabled or not
// <id> dfll_arch_bplckc
#ifndef CONF_DFLL_BPLCKC
#define CONF_DFLL_BPLCKC 0
#endif
// <q> Quick Lock Disable
// <i> Indicates whether Quick Lock Disable is enabled or not
// <id> dfll_arch_qldis
#ifndef CONF_DFLL_QLDIS
#define CONF_DFLL_QLDIS 0
#endif
// <q> Chill Cycle Disable
// <i> Indicates whether Chill Cycle Disable is enabled or not
// <id> dfll_arch_ccdis
#ifndef CONF_DFLL_CCDIS
#define CONF_DFLL_CCDIS 0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> dfll_arch_ondemand
#ifndef CONF_DFLL_ONDEMAND
#define CONF_DFLL_ONDEMAND 1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> dfll_arch_runstdby
#ifndef CONF_DFLL_RUNSTDBY
#define CONF_DFLL_RUNSTDBY 0
#endif
// <q> USB Clock Recovery Mode
// <i> Indicates whether USB Clock Recovery Mode is enabled or not
// <id> dfll_arch_usbcrm
#ifndef CONF_DFLL_USBCRM
#define CONF_DFLL_USBCRM 0
#endif
// <q> Lose Lock After Wake
// <i> Indicates whether Lose Lock After Wake is enabled or not
// <id> dfll_arch_llaw
#ifndef CONF_DFLL_LLAW
#define CONF_DFLL_LLAW 0
#endif
// <q> Stable DFLL Frequency
// <i> Indicates whether Stable DFLL Frequency is enabled or not
// <id> dfll_arch_stable
#ifndef CONF_DFLL_STABLE
#define CONF_DFLL_STABLE 0
#endif
// <o> Operating Mode Selection
// <0=>Open Loop Mode
// <1=>Closed Loop Mode
// <id> dfll48m_mode
#ifndef CONF_DFLL_MODE
#define CONF_DFLL_MODE 0
#endif
// <o> Coarse Maximum Step <0x0-0x1F>
// <id> dfll_arch_cstep
#ifndef CONF_DFLL_CSTEP
#define CONF_DFLL_CSTEP 1
#endif
// <o> Fine Maximum Step <0x0-0x3FF>
// <id> dfll_arch_fstep
#ifndef CONF_DFLL_FSTEP
#define CONF_DFLL_FSTEP 1
#endif
// <o> DFLL Multiply Factor <0x0-0xFFFF>
// <id> dfll48m_mul
#ifndef CONF_DFLL_MUL
#define CONF_DFLL_MUL 0
#endif
// <e> DFLL Calibration Overwrite
// <i> Indicates whether Overwrite Calibration value of DFLL
// <id> dfll_arch_calibration
#ifndef CONF_DFLL_OVERWRITE_CALIBRATION
#define CONF_DFLL_OVERWRITE_CALIBRATION 0
#endif
// <o> Coarse Value <0x0-0x3F>
// <id> dfll_arch_coarse
#ifndef CONF_DFLL_COARSE
#define CONF_DFLL_COARSE (0x1f / 4)
#endif
// <o> Fine Value <0x0-0x3FF>
// <id> dfll_arch_fine
#ifndef CONF_DFLL_FINE
#define CONF_DFLL_FINE (0x200)
#endif
//</e>
//</h>
//</e>
// <e> DPLL Configuration
// <i> Indicates whether configuration for DPLL is enabled or not
// <id> enable_fdpll96m
#ifndef CONF_DPLL_CONFIG
#define CONF_DPLL_CONFIG 0
#endif
// <y> Reference Clock Source
// <GCLK_GENCTRL_SRC_XOSC32K"> 32kHz External Crystal Oscillator (XOSC32K)
// <GCLK_GENCTRL_SRC_XOSC"> External Crystal Oscillator 0.4-32MHz (XOSC)
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <GCLK_PCHCTRL_GEN_GCLK5_Val"> Generic clock generator 5
// <GCLK_PCHCTRL_GEN_GCLK6_Val"> Generic clock generator 6
// <GCLK_PCHCTRL_GEN_GCLK7_Val"> Generic clock generator 7
// <i> Select the clock source.
// <id> fdpll96m_ref_clock
#ifndef CONF_DPLL_GCLK
#define CONF_DPLL_GCLK GCLK_GENCTRL_SRC_XOSC32K
#endif
// <h> Digital Phase Locked Loop Control
// <q> Enable
// <i> Indicates whether Digital Phase Locked Loop is enabled or not
// <id> fdpll96m_arch_enable
#ifndef CONF_DPLL_ENABLE
#define CONF_DPLL_ENABLE 0
#endif
// <q> On Demand Control
// <i> Indicates whether On Demand Control is enabled or not
// <id> fdpll96m_arch_ondemand
#ifndef CONF_DPLL_ONDEMAND
#define CONF_DPLL_ONDEMAND 1
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> fdpll96m_arch_runstdby
#ifndef CONF_DPLL_RUNSTDBY
#define CONF_DPLL_RUNSTDBY 0
#endif
// <o> Loop Divider Ratio Fractional Part <0x0-0xF>
// <id> fdpll96m_ldrfrac
#ifndef CONF_DPLL_LDRFRAC
#define CONF_DPLL_LDRFRAC 0xd
#endif
// <o> Loop Divider Ratio Integer Part <0x0-0xFFF>
// <id> fdpll96m_ldr
#ifndef CONF_DPLL_LDR
#define CONF_DPLL_LDR 0x5b7
#endif
// <o> Clock Divider <0x0-0x3FF>
// <id> fdpll96m_clock_div
#ifndef CONF_DPLL_DIV
#define CONF_DPLL_DIV 0
#endif
// <q> Lock Bypass
// <i> Indicates whether Lock Bypass is enabled or not
// <id> fdpll96m_arch_lbypass
#ifndef CONF_DPLL_LBYPASS
#define CONF_DPLL_LBYPASS 0
#endif
// <o> Lock Time
// <0=>No time-out, automatic lock
// <4=>The Time-out if no lock within 8 ms
// <5=>The Time-out if no lock within 9 ms
// <6=>The Time-out if no lock within 10 ms
// <7=>The Time-out if no lock within 11 ms
// <id> fdpll96m_arch_ltime
#ifndef CONF_DPLL_LTIME
#define CONF_DPLL_LTIME 0
#endif
// <o> Reference Clock Selection
// <0=>XOSC32K clock reference
// <1=>XOSC clock reference
// <2=>GCLK clock reference
// <id> fdpll96m_arch_refclk
#ifndef CONF_DPLL_REFCLK
#define CONF_DPLL_REFCLK 0
#endif
// <q> Wake Up Fast
// <i> Indicates whether Wake Up Fast is enabled or not
// <id> fdpll96m_arch_wuf
#ifndef CONF_DPLL_WUF
#define CONF_DPLL_WUF 0
#endif
// <q> Low-Power Enable
// <i> Indicates whether Low-Power Enable is enabled or not
// <id> fdpll96m_arch_lpen
#ifndef CONF_DPLL_LPEN
#define CONF_DPLL_LPEN 0
#endif
// <o> Reference Clock Selection
// <0=>Default filter mode
// <1=>Low bandwidth filter
// <2=>High bandwidth filter
// <3=>High damping filter
// <id> fdpll96m_arch_filter
#ifndef CONF_DPLL_FILTER
#define CONF_DPLL_FILTER 0
#endif
// <y> Output Clock Prescaler
// <OSCCTRL_DPLLPRESC_PRESC_DIV1_Val"> 1
// <OSCCTRL_DPLLPRESC_PRESC_DIV2_Val"> 2
// <OSCCTRL_DPLLPRESC_PRESC_DIV4_Val"> 4
// <id> fdpll96m_presc
#ifndef CONF_DPLL_PRESC
#define CONF_DPLL_PRESC OSCCTRL_DPLLPRESC_PRESC_DIV1_Val
#endif
//</h>
//</e>
// <<< end of configuration section >>>
#endif // HPL_OSCCTRL_CONFIG_H

284
Smol Watch Project/My Project/Config/hpl_port_config.h
View file

@ -1,284 +0,0 @@
/* Auto-generated config file hpl_port_config.h */
#ifndef HPL_PORT_CONFIG_H
#define HPL_PORT_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <e> PORT Input Event 0 configuration
// <id> enable_port_input_event_0
#ifndef CONF_PORT_EVCTRL_PORT_0
#define CONF_PORT_EVCTRL_PORT_0 0
#endif
// <h> PORT Input Event 0 configuration on PORT A
// <q> PORTA Input Event 0 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 0 configuration is enabled
// <id> porta_input_event_enable_0
#ifndef CONF_PORTA_EVCTRL_PORTEI_0
#define CONF_PORTA_EVCTRL_PORTEI_0 0x0
#endif
// <o> PORTA Event 0 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_0
#ifndef CONF_PORTA_EVCTRL_PID_0
#define CONF_PORTA_EVCTRL_PID_0 0x0
#endif
// <o> PORTA Event 0 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 0
// <id> porta_event_action_0
#ifndef CONF_PORTA_EVCTRL_EVACT_0
#define CONF_PORTA_EVCTRL_EVACT_0 0
#endif
// </h>
// <h> PORT Input Event 0 configuration on PORT B
// <q> PORTB Input Event 0 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 0 configuration is enabled
// <id> portb_input_event_enable_0
#ifndef CONF_PORTB_EVCTRL_PORTEI_0
#define CONF_PORTB_EVCTRL_PORTEI_0 0x0
#endif
// <o> PORTB Event 0 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_0
#ifndef CONF_PORTB_EVCTRL_PID_0
#define CONF_PORTB_EVCTRL_PID_0 0x0
#endif
// <o> PORTB Event 0 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 0
// <id> portb_event_action_0
#ifndef CONF_PORTB_EVCTRL_EVACT_0
#define CONF_PORTB_EVCTRL_EVACT_0 0
#endif
// </h>
// </e>
// <e> PORT Input Event 1 configuration
// <id> enable_port_input_event_1
#ifndef CONF_PORT_EVCTRL_PORT_1
#define CONF_PORT_EVCTRL_PORT_1 0
#endif
// <h> PORT Input Event 1 configuration on PORT A
// <q> PORTA Input Event 1 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 1 configuration is enabled
// <id> porta_input_event_enable_1
#ifndef CONF_PORTA_EVCTRL_PORTEI_1
#define CONF_PORTA_EVCTRL_PORTEI_1 0x0
#endif
// <o> PORTA Event 1 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_1
#ifndef CONF_PORTA_EVCTRL_PID_1
#define CONF_PORTA_EVCTRL_PID_1 0x0
#endif
// <o> PORTA Event 1 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 1
// <id> porta_event_action_1
#ifndef CONF_PORTA_EVCTRL_EVACT_1
#define CONF_PORTA_EVCTRL_EVACT_1 0
#endif
// </h>
// <h> PORT Input Event 1 configuration on PORT B
// <q> PORTB Input Event 1 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 1 configuration is enabled
// <id> portb_input_event_enable_1
#ifndef CONF_PORTB_EVCTRL_PORTEI_1
#define CONF_PORTB_EVCTRL_PORTEI_1 0x0
#endif
// <o> PORTB Event 1 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_1
#ifndef CONF_PORTB_EVCTRL_PID_1
#define CONF_PORTB_EVCTRL_PID_1 0x0
#endif
// <o> PORTB Event 1 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 1
// <id> portb_event_action_1
#ifndef CONF_PORTB_EVCTRL_EVACT_1
#define CONF_PORTB_EVCTRL_EVACT_1 0
#endif
// </h>
// </e>
// <e> PORT Input Event 2 configuration
// <id> enable_port_input_event_2
#ifndef CONF_PORT_EVCTRL_PORT_2
#define CONF_PORT_EVCTRL_PORT_2 0
#endif
// <h> PORT Input Event 2 configuration on PORT A
// <q> PORTA Input Event 2 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 2 configuration is enabled
// <id> porta_input_event_enable_2
#ifndef CONF_PORTA_EVCTRL_PORTEI_2
#define CONF_PORTA_EVCTRL_PORTEI_2 0x0
#endif
// <o> PORTA Event 2 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_2
#ifndef CONF_PORTA_EVCTRL_PID_2
#define CONF_PORTA_EVCTRL_PID_2 0x0
#endif
// <o> PORTA Event 2 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 2
// <id> porta_event_action_2
#ifndef CONF_PORTA_EVCTRL_EVACT_2
#define CONF_PORTA_EVCTRL_EVACT_2 0
#endif
// </h>
// <h> PORT Input Event 2 configuration on PORT B
// <q> PORTB Input Event 2 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 2 configuration is enabled
// <id> portb_input_event_enable_2
#ifndef CONF_PORTB_EVCTRL_PORTEI_2
#define CONF_PORTB_EVCTRL_PORTEI_2 0x0
#endif
// <o> PORTB Event 2 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_2
#ifndef CONF_PORTB_EVCTRL_PID_2
#define CONF_PORTB_EVCTRL_PID_2 0x0
#endif
// <o> PORTB Event 2 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 2
// <id> portb_event_action_2
#ifndef CONF_PORTB_EVCTRL_EVACT_2
#define CONF_PORTB_EVCTRL_EVACT_2 0
#endif
// </h>
// </e>
// <e> PORT Input Event 3 configuration
// <id> enable_port_input_event_3
#ifndef CONF_PORT_EVCTRL_PORT_3
#define CONF_PORT_EVCTRL_PORT_3 0
#endif
// <h> PORT Input Event 3 configuration on PORT A
// <q> PORTA Input Event 3 Enable
// <i> The event action will be triggered on any incoming event if PORT A Input Event 3 configuration is enabled
// <id> porta_input_event_enable_3
#ifndef CONF_PORTA_EVCTRL_PORTEI_3
#define CONF_PORTA_EVCTRL_PORTEI_3 0x0
#endif
// <o> PORTA Event 3 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port A on which the event action will be performed
// <id> porta_event_pin_identifier_3
#ifndef CONF_PORTA_EVCTRL_PID_3
#define CONF_PORTA_EVCTRL_PID_3 0x0
#endif
// <o> PORTA Event 3 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT A will perform on event input 3
// <id> porta_event_action_3
#ifndef CONF_PORTA_EVCTRL_EVACT_3
#define CONF_PORTA_EVCTRL_EVACT_3 0
#endif
// </h>
// <h> PORT Input Event 3 configuration on PORT B
// <q> PORTB Input Event 3 Enable
// <i> The event action will be triggered on any incoming event if PORT B Input Event 3 configuration is enabled
// <id> portb_input_event_enable_3
#ifndef CONF_PORTB_EVCTRL_PORTEI_3
#define CONF_PORTB_EVCTRL_PORTEI_3 0x0
#endif
// <o> PORTB Event 3 Pin Identifier <0x00-0x1F>
// <i> These bits define the I/O pin from port B on which the event action will be performed
// <id> portb_event_pin_identifier_3
#ifndef CONF_PORTB_EVCTRL_PID_3
#define CONF_PORTB_EVCTRL_PID_3 0x0
#endif
// <o> PORTB Event 3 Action
// <0=> Output register of pin will be set to level of event
// <1=> Set output register of pin on event
// <2=> Clear output register of pin on event
// <3=> Toggle output register of pin on event
// <i> These bits define the event action the PORT B will perform on event input 3
// <id> portb_event_action_3
#ifndef CONF_PORTB_EVCTRL_EVACT_3
#define CONF_PORTB_EVCTRL_EVACT_3 0
#endif
// </h>
// </e>
#define CONF_PORTA_EVCTRL \
(0 | PORT_EVCTRL_EVACT0(CONF_PORTA_EVCTRL_EVACT_0) | CONF_PORTA_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
| PORT_EVCTRL_PID0(CONF_PORTA_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTA_EVCTRL_EVACT_1) \
| CONF_PORTA_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTA_EVCTRL_PID_1) \
| PORT_EVCTRL_EVACT2(CONF_PORTA_EVCTRL_EVACT_2) | CONF_PORTA_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
| PORT_EVCTRL_PID2(CONF_PORTA_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTA_EVCTRL_EVACT_3) \
| CONF_PORTA_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTA_EVCTRL_PID_3))
#define CONF_PORTB_EVCTRL \
(0 | PORT_EVCTRL_EVACT0(CONF_PORTB_EVCTRL_EVACT_0) | CONF_PORTB_EVCTRL_PORTEI_0 << PORT_EVCTRL_PORTEI0_Pos \
| PORT_EVCTRL_PID0(CONF_PORTB_EVCTRL_PID_0) | PORT_EVCTRL_EVACT1(CONF_PORTB_EVCTRL_EVACT_1) \
| CONF_PORTB_EVCTRL_PORTEI_1 << PORT_EVCTRL_PORTEI1_Pos | PORT_EVCTRL_PID1(CONF_PORTB_EVCTRL_PID_1) \
| PORT_EVCTRL_EVACT2(CONF_PORTB_EVCTRL_EVACT_2) | CONF_PORTB_EVCTRL_PORTEI_2 << PORT_EVCTRL_PORTEI2_Pos \
| PORT_EVCTRL_PID2(CONF_PORTB_EVCTRL_PID_2) | PORT_EVCTRL_EVACT3(CONF_PORTB_EVCTRL_EVACT_3) \
| CONF_PORTB_EVCTRL_PORTEI_3 << PORT_EVCTRL_PORTEI3_Pos | PORT_EVCTRL_PID3(CONF_PORTB_EVCTRL_PID_3))
// <<< end of configuration section >>>
#endif // HPL_PORT_CONFIG_H

318
Smol Watch Project/My Project/Config/hpl_rtc_config.h
View file

@ -1,318 +0,0 @@
/* Auto-generated config file hpl_rtc_config.h */
#ifndef HPL_RTC_CONFIG_H
#define HPL_RTC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Basic settings
#ifndef CONF_RTC_ENABLE
#define CONF_RTC_ENABLE 1
#endif
// <q> Force reset RTC on initialization
// <i> Force RTC to reset on initialization.
// <i> Note that the previous power down data in RTC is lost if it's enabled.
// <id> rtc_arch_init_reset
#ifndef CONF_RTC_INIT_RESET
#define CONF_RTC_INIT_RESET 0
#endif
// <o> Prescaler configuration
// <0x0=>OFF(Peripheral clock divided by 1)
// <0x1=>Peripheral clock divided by 1
// <0x2=>Peripheral clock divided by 2
// <0x3=>Peripheral clock divided by 4
// <0x4=>Peripheral clock divided by 8
// <0x5=>Peripheral clock divided by 16
// <0x6=>Peripheral clock divided by 32
// <0x7=>Peripheral clock divided by 64
// <0x8=>Peripheral clock divided by 128
// <0x9=>Peripheral clock divided by 256
// <0xA=>Peripheral clock divided by 512
// <0xB=>Peripheral clock divided by 1024
// <i> These bits define the RTC clock relative to the peripheral clock
// <id> rtc_arch_prescaler
#ifndef CONF_RTC_PRESCALER
#define CONF_RTC_PRESCALER 0xb
#endif
#ifndef CONF_RTC_COMP_VAL
#define CONF_RTC_COMP_VAL 0
#endif
// <e> RTC Tamper Input 0 settings
// <id> tamper_input_0_settings
#ifndef CONF_TAMPER_INPUT_0_SETTINGS
#define CONF_TAMPER_INPUT_0_SETTINGS 0
#endif
// <q> Tamper Level Settings
// <i> Indicates Tamper input 0 level
// <id> tamper_level_0
#ifndef CONF_RTC_TAMP_LVL_0
#define CONF_RTC_TAMP_LVL_0 0
#endif
// <o> RTC Tamper Input Action
// <0x0=>OFF(Disabled)
// <0x1=>Wake and Set Tamper Flag
// <0x2=>Capture Timestamp and Set Tamper Flag
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
// <i> These bits define the RTC Tamper Input Action to be performed
// <id> rtc_tamper_input_action_0
#ifndef CONF_RTC_TAMPER_INACT_0
#define CONF_RTC_TAMPER_INACT_0 0
#endif
// <q> Debounce Enable for Tamper Input
// <i> Indicates Debounce should be enabled for Tamper input 0
// <id> tamper_debounce_enable_0
#ifndef CONF_RTC_TAMP_DEBNC_0
#define CONF_RTC_TAMP_DEBNC_0 0
#endif
// </e>
// <e> RTC Tamper Input 1 settings
// <id> tamper_input_1_settings
#ifndef CONF_TAMPER_INPUT_1_SETTINGS
#define CONF_TAMPER_INPUT_1_SETTINGS 0
#endif
// <q> Tamper Level Settings
// <i> Indicates Tamper input 1 level
// <id> tamper_level_1
#ifndef CONF_RTC_TAMP_LVL_1
#define CONF_RTC_TAMP_LVL_1 0
#endif
// <o> RTC Tamper Input Action
// <0x0=>OFF(Disabled)
// <0x1=>Wake and Set Tamper Flag
// <0x2=>Capture Timestamp and Set Tamper Flag
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
// <i> These bits define the RTC Tamper Input Action to be performed
// <id> rtc_tamper_input_action_1
#ifndef CONF_RTC_TAMPER_INACT_1
#define CONF_RTC_TAMPER_INACT_1 0
#endif
// <q> Debounce Enable for Tamper Input
// <i> Indicates Debounce should be enabled for Tamper input 1
// <id> tamper_debounce_enable_1
#ifndef CONF_RTC_TAMP_DEBNC_1
#define CONF_RTC_TAMP_DEBNC_1 0
#endif
// </e>
// <e> RTC Tamper Input 2 settings
// <id> tamper_input_2_settings
#ifndef CONF_TAMPER_INPUT_2_SETTINGS
#define CONF_TAMPER_INPUT_2_SETTINGS 0
#endif
// <q> Tamper Level Settings
// <i> Indicates Tamper input 2 level
// <id> tamper_level_2
#ifndef CONF_RTC_TAMP_LVL_2
#define CONF_RTC_TAMP_LVL_2 0
#endif
// <o> RTC Tamper Input Action
// <0x0=>OFF(Disabled)
// <0x1=>Wake and Set Tamper Flag
// <0x2=>Capture Timestamp and Set Tamper Flag
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
// <i> These bits define the RTC Tamper Input Action to be performed
// <id> rtc_tamper_input_action_2
#ifndef CONF_RTC_TAMPER_INACT_2
#define CONF_RTC_TAMPER_INACT_2 0
#endif
// <q> Debounce Enable for Tamper Input
// <i> Indicates Debounce should be enabled for Tamper input 2
// <id> tamper_debounce_enable_2
#ifndef CONF_RTC_TAMP_DEBNC_2
#define CONF_RTC_TAMP_DEBNC_2 0
#endif
// </e>
// <e> RTC Tamper Input 3 settings
// <id> tamper_input_3_settings
#ifndef CONF_TAMPER_INPUT_3_SETTINGS
#define CONF_TAMPER_INPUT_3_SETTINGS 0
#endif
// <q> Tamper Level Settings
// <i> Indicates Tamper input 3 level
// <id> tamper_level_3
#ifndef CONF_RTC_TAMP_LVL_3
#define CONF_RTC_TAMP_LVL_3 0
#endif
// <o> RTC Tamper Input Action
// <0x0=>OFF(Disabled)
// <0x1=>Wake and Set Tamper Flag
// <0x2=>Capture Timestamp and Set Tamper Flag
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
// <i> These bits define the RTC Tamper Input Action to be performed
// <id> rtc_tamper_input_action_3
#ifndef CONF_RTC_TAMPER_INACT_3
#define CONF_RTC_TAMPER_INACT_3 0
#endif
// <q> Debounce Enable for Tamper Input
// <i> Indicates Debounce should be enabled for Tamper input 3
// <id> tamper_debounce_enable_3
#ifndef CONF_RTC_TAMP_DEBNC_3
#define CONF_RTC_TAMP_DEBNC_3 0
#endif
// </e>
// <e> RTC Tamper Input 4 settings
// <id> tamper_input_4_settings
#ifndef CONF_TAMPER_INPUT_4_SETTINGS
#define CONF_TAMPER_INPUT_4_SETTINGS 0
#endif
// <q> Tamper Level Settings
// <i> Indicates Tamper input 4 level
// <id> tamper_level_4
#ifndef CONF_RTC_TAMP_LVL_4
#define CONF_RTC_TAMP_LVL_4 0
#endif
// <o> RTC Tamper Input Action
// <0x0=>OFF(Disabled)
// <0x1=>Wake and Set Tamper Flag
// <0x2=>Capture Timestamp and Set Tamper Flag
// <0x3=>Active Layer Mode.IN and OUT pin is used.Timestamp is also captured.
// <i> These bits define the RTC Tamper Input Action to be performed
// <id> rtc_tamper_input_action_4
#ifndef CONF_RTC_TAMPER_INACT_4
#define CONF_RTC_TAMPER_INACT_4 0
#endif
// <q> Debounce Enable for Tamper Input
// <i> Indicates Debounce should be enabled for Tamper input 4
// <id> tamper_debounce_enable_4
#ifndef CONF_RTC_TAMP_DEBNC_4
#define CONF_RTC_TAMP_DEBNC_4 0
#endif
// </e>
// <o> RTC Tamper Active Layer Frequency Prescalar
// <0x0=>DIV2 CLK_RTC_OUT is CLK_RTC /2
// <0x1=>DIV4 CLK_RTC_OUT is CLK_RTC /4
// <0x2=>DIV8 CLK_RTC_OUT is CLK_RTC /8
// <0x3=>DIV16 CLK_RTC_OUT is CLK_RTC /16
// <0x4=>DIV32 CLK_RTC_OUT is CLK_RTC /32
// <0x5=>DIV64 CLK_RTC_OUT is CLK_RTC /64
// <0x6=>DIV128 CLK_RTC_OUT is CLK_RTC /128
// <0x7=>DIV256 CLK_RTC_OUT is CLK_RTC /256
// <i> These bits define the RTC Tamper Active Layer Frequecny Prescalar
// <id> rtc_tamper_active_layer_frequency_prescalar
#ifndef CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES
#define CONF_RTC_TAMP_ACT_LAYER_FREQ_PRES 0
#endif
// <o> RTC Tamper Debounce Frequency Prescalar
// <0x0=>DIV2 CLK_RTC_DEB is CLK_RTC /2
// <0x1=>DIV4 CLK_RTC_DEB is CLK_RTC /4
// <0x2=>DIV8 CLK_RTC_DEB is CLK_RTC /8
// <0x3=>DIV16 CLK_RTC_DEB is CLK_RTC /16
// <0x4=>DIV32 CLK_RTC_DEB is CLK_RTC /32
// <0x5=>DIV64 CLK_RTC_DEB is CLK_RTC /64
// <0x6=>DIV128 CLK_RTC_DEB is CLK_RTC /128
// <0x7=>DIV256 CLK_RTC_DEB is CLK_RTC /256
// <i> These bits define the RTC Debounce Frequency Prescalar
// <id> rtc_tamper_debounce_frequency_prescalar
#ifndef CONF_RTC_TAMP_DEBF_PRES
#define CONF_RTC_TAMP_DEBF_PRES 0
#endif
// <e> Event control
// <id> rtc_event_control
#ifndef CONF_RTC_EVENT_CONTROL_ENABLE
#define CONF_RTC_EVENT_CONTROL_ENABLE 0
#endif
// <q> Periodic Interval 0 Event Output
// <i> This bit indicates whether Periodic interval 0 event is enabled and will be generated
// <id> rtc_pereo0
#ifndef CONF_RTC_PEREO0
#define CONF_RTC_PEREO0 0
#endif
// <q> Periodic Interval 1 Event Output
// <i> This bit indicates whether Periodic interval 1 event is enabled and will be generated
// <id> rtc_pereo1
#ifndef CONF_RTC_PEREO1
#define CONF_RTC_PEREO1 0
#endif
// <q> Periodic Interval 2 Event Output
// <i> This bit indicates whether Periodic interval 2 event is enabled and will be generated
// <id> rtc_pereo2
#ifndef CONF_RTC_PEREO2
#define CONF_RTC_PEREO2 0
#endif
// <q> Periodic Interval 3 Event Output
// <i> This bit indicates whether Periodic interval 3 event is enabled and will be generated
// <id> rtc_pereo3
#ifndef CONF_RTC_PEREO3
#define CONF_RTC_PEREO3 0
#endif
// <q> Periodic Interval 4 Event Output
// <i> This bit indicates whether Periodic interval 4 event is enabled and will be generated
// <id> rtc_pereo4
#ifndef CONF_RTC_PEREO4
#define CONF_RTC_PEREO4 0
#endif
// <q> Periodic Interval 5 Event Output
// <i> This bit indicates whether Periodic interval 5 event is enabled and will be generated
// <id> rtc_pereo5
#ifndef CONF_RTC_PEREO5
#define CONF_RTC_PEREO5 0
#endif
// <q> Periodic Interval 6 Event Output
// <i> This bit indicates whether Periodic interval 6 event is enabled and will be generated
// <id> rtc_pereo6
#ifndef CONF_RTC_PEREO6
#define CONF_RTC_PEREO6 0
#endif
// <q> Periodic Interval 7 Event Output
// <i> This bit indicates whether Periodic interval 7 event is enabled and will be generated
// <id> rtc_pereo7
#ifndef CONF_RTC_PEREO7
#define CONF_RTC_PEREO7 0
#endif
// <q> Compare 0 Event Output
// <i> This bit indicates whether Compare O event is enabled and will be generated
// <id> rtc_cmpeo0
#ifndef CONF_RTC_COMPE0
#define CONF_RTC_COMPE0 0
#endif
// <q> Overflow Event Output
// <i> This bit indicates whether Overflow event is enabled and will be generated
// <id> rtc_ovfeo
#ifndef CONF_RTC_OVFEO
#define CONF_RTC_OVFEO 0
#endif
// </e>
// </h>
// <<< end of configuration section >>>
#endif // HPL_RTC_CONFIG_H

144
Smol Watch Project/My Project/Config/hpl_sercom_config.h
View file

@ -1,144 +0,0 @@
/* Auto-generated config file hpl_sercom_config.h */
#ifndef HPL_SERCOM_CONFIG_H
#define HPL_SERCOM_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
#ifndef SERCOM_I2CM_CTRLA_MODE_I2C_MASTER
#define SERCOM_I2CM_CTRLA_MODE_I2C_MASTER (5 << 2)
#endif
#ifndef CONF_SERCOM_1_I2CM_ENABLE
#define CONF_SERCOM_1_I2CM_ENABLE 1
#endif
// <h> Basic
// <o> I2C Bus clock speed (Hz) <1-400000>
// <i> I2C Bus clock (SCL) speed measured in Hz
// <id> i2c_master_baud_rate
#ifndef CONF_SERCOM_1_I2CM_BAUD
#define CONF_SERCOM_1_I2CM_BAUD 100000
#endif
// </h>
// <e> Advanced
// <id> i2c_master_advanced
#ifndef CONF_SERCOM_1_I2CM_ADVANCED_CONFIG
#define CONF_SERCOM_1_I2CM_ADVANCED_CONFIG 0
#endif
// <o> TRise (ns) <0-300>
// <i> Determined by the bus impedance, check electric characteristics in the datasheet
// <i> Standard Fast Mode: typical 215ns, max 300ns
// <i> Fast Mode +: typical 60ns, max 100ns
// <i> High Speed Mode: typical 20ns, max 40ns
// <id> i2c_master_arch_trise
#ifndef CONF_SERCOM_1_I2CM_TRISE
#define CONF_SERCOM_1_I2CM_TRISE 215
#endif
// <q> Master SCL Low Extended Time-Out (MEXTTOEN)
// <i> This enables the master SCL low extend time-out
// <id> i2c_master_arch_mexttoen
#ifndef CONF_SERCOM_1_I2CM_MEXTTOEN
#define CONF_SERCOM_1_I2CM_MEXTTOEN 0
#endif
// <q> Slave SCL Low Extend Time-Out (SEXTTOEN)
// <i> Enables the slave SCL low extend time-out. If SCL is cumulatively held low for greater than 25ms from the initial START to a STOP, the slave will release its clock hold if enabled and reset the internal state machine
// <id> i2c_master_arch_sexttoen
#ifndef CONF_SERCOM_1_I2CM_SEXTTOEN
#define CONF_SERCOM_1_I2CM_SEXTTOEN 0
#endif
// <q> SCL Low Time-Out (LOWTOUT)
// <i> Enables SCL low time-out. If SCL is held low for 25ms-35ms, the master will release it's clock hold
// <id> i2c_master_arch_lowtout
#ifndef CONF_SERCOM_1_I2CM_LOWTOUT
#define CONF_SERCOM_1_I2CM_LOWTOUT 0
#endif
// <o> Inactive Time-Out (INACTOUT)
// <0x0=>Disabled
// <0x1=>5-6 SCL cycle time-out(50-60us)
// <0x2=>10-11 SCL cycle time-out(100-110us)
// <0x3=>20-21 SCL cycle time-out(200-210us)
// <i> Defines if inactivity time-out should be enabled, and how long the time-out should be
// <id> i2c_master_arch_inactout
#ifndef CONF_SERCOM_1_I2CM_INACTOUT
#define CONF_SERCOM_1_I2CM_INACTOUT 0x0
#endif
// <o> SDA Hold Time (SDAHOLD)
// <0=>Disabled
// <1=>50-100ns hold time
// <2=>300-600ns hold time
// <3=>400-800ns hold time
// <i> Defines the SDA hold time with respect to the negative edge of SCL
// <id> i2c_master_arch_sdahold
#ifndef CONF_SERCOM_1_I2CM_SDAHOLD
#define CONF_SERCOM_1_I2CM_SDAHOLD 0x2
#endif
// <q> Run in stand-by
// <i> Determine if the module shall run in standby sleep mode
// <id> i2c_master_arch_runstdby
#ifndef CONF_SERCOM_1_I2CM_RUNSTDBY
#define CONF_SERCOM_1_I2CM_RUNSTDBY 0
#endif
// <o> Debug Stop Mode
// <i> Behavior of the baud-rate generator when CPU is halted by external debugger.
// <0=>Keep running
// <1=>Halt
// <id> i2c_master_arch_dbgstop
#ifndef CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE
#define CONF_SERCOM_1_I2CM_DEBUG_STOP_MODE 0
#endif
// </e>
#ifndef CONF_SERCOM_1_I2CM_SPEED
#define CONF_SERCOM_1_I2CM_SPEED 0x00 // Speed: Standard/Fast mode
#endif
#if CONF_SERCOM_1_I2CM_TRISE < 215 || CONF_SERCOM_1_I2CM_TRISE > 300
#warning Bad I2C Rise time for Standard/Fast mode, reset to 215ns
#undef CONF_SERCOM_1_I2CM_TRISE
#define CONF_SERCOM_1_I2CM_TRISE 215U
#endif
// gclk_freq - (i2c_scl_freq * 10) - (gclk_freq * i2c_scl_freq * Trise)
// BAUD + BAUDLOW = --------------------------------------------------------------------
// i2c_scl_freq
// BAUD: register value low [7:0]
// BAUDLOW: register value high [15:8], only used for odd BAUD + BAUDLOW
#define CONF_SERCOM_1_I2CM_BAUD_BAUDLOW \
(((CONF_GCLK_SERCOM1_CORE_FREQUENCY - (CONF_SERCOM_1_I2CM_BAUD * 10U) \
- (CONF_SERCOM_1_I2CM_TRISE * (CONF_SERCOM_1_I2CM_BAUD / 100U) * (CONF_GCLK_SERCOM1_CORE_FREQUENCY / 10000U) \
/ 1000U)) \
* 10U \
+ 5U) \
/ (CONF_SERCOM_1_I2CM_BAUD * 10U))
#ifndef CONF_SERCOM_1_I2CM_BAUD_RATE
#if CONF_SERCOM_1_I2CM_BAUD_BAUDLOW > (0xFF * 2)
#warning Requested I2C baudrate too low, please check
#define CONF_SERCOM_1_I2CM_BAUD_RATE 0xFF
#elif CONF_SERCOM_1_I2CM_BAUD_BAUDLOW <= 1
#warning Requested I2C baudrate too high, please check
#define CONF_SERCOM_1_I2CM_BAUD_RATE 1
#else
#define CONF_SERCOM_1_I2CM_BAUD_RATE \
((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW & 0x1) \
? (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2) + ((CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2 + 1) << 8) \
: (CONF_SERCOM_1_I2CM_BAUD_BAUDLOW / 2))
#endif
#endif
// <<< end of configuration section >>>
#endif // HPL_SERCOM_CONFIG_H

2744
Smol Watch Project/My Project/Config/hpl_slcd_config.h
View file

File diff suppressed because it is too large Load diff

18
Smol Watch Project/My Project/Config/hpl_systick_config.h
View file

@ -1,18 +0,0 @@
/* Auto-generated config file hpl_systick_config.h */
#ifndef HPL_SYSTICK_CONFIG_H
#define HPL_SYSTICK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <h> Advanced settings
// <q> SysTick exception request
// <i> Indicates whether the generation of SysTick exception is enabled or not
// <id> systick_arch_tickint
#ifndef CONF_SYSTICK_TICKINT
#define CONF_SYSTICK_TICKINT 0
#endif
// </h>
// <<< end of configuration section >>>
#endif // HPL_SYSTICK_CONFIG_H

547
Smol Watch Project/My Project/Config/hpl_tcc_config.h
View file

@ -1,547 +0,0 @@
/* Auto-generated config file hpl_tcc_config.h */
#ifndef HPL_TCC_CONFIG_H
#define HPL_TCC_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
#include <peripheral_clk_config.h>
#ifndef CONF_TCC0_ENABLE
#define CONF_TCC0_ENABLE 1
#endif
#ifndef CONF_TCC0_PWM_ENABLE
#define CONF_TCC0_PWM_ENABLE 1
#endif
// <h> Basic settings
// <y> TCC0 Prescaler
// <TCC_CTRLA_PRESCALER_DIV1_Val"> No division
// <TCC_CTRLA_PRESCALER_DIV2_Val"> Divide by 2
// <TCC_CTRLA_PRESCALER_DIV4_Val"> Divide by 4
// <TCC_CTRLA_PRESCALER_DIV8_Val"> Divide by 8
// <TCC_CTRLA_PRESCALER_DIV16_Val"> Divide by 16
// <TCC_CTRLA_PRESCALER_DIV64_Val"> Divide by 64
// <TCC_CTRLA_PRESCALER_DIV256_Val"> Divide by 256
// <TCC_CTRLA_PRESCALER_DIV1024_Val"> Divide by 1024
// <i> This defines the TCC0 prescaler value
// <id> tcc_prescaler
#ifndef CONF_TCC0_PRESCALER
#define CONF_TCC0_PRESCALER TCC_CTRLA_PRESCALER_DIV8_Val
#endif
// <hidden>
//<o> TCC0 Period Value <0x000000-0xFFFFFF>
// <id> tcc_per
#ifndef CONF_TCC0_PER
#define CONF_TCC0_PER 0x2710
#endif
// </hidden>
// </h>
// <h> PWM Waveform Output settings
// <o> TCC0 Waveform Period Value (uS) <0x00-0xFFFFFFFF>
// <i> The unit of this value is us.
// <id> tcc_arch_wave_per_val
#ifndef CONF_TCC0_WAVE_PER_VAL
#define CONF_TCC0_WAVE_PER_VAL 0x3e8
#endif
// <o> TCC0 Waveform Duty Value (0.1%) <0x00-0x03E8>
// <i> The unit of this value is 1/1000.
// <id> tcc_arch_wave_duty_val
#ifndef CONF_TCC0_WAVE_DUTY_VAL
#define CONF_TCC0_WAVE_DUTY_VAL 0x1f4
#endif
// <o> TCC0 Waveform Channel Select <0x00-0x03>
// <i> Index of the Compare Channel register, into which the Waveform Duty Value is written.
// <i> Give index of the Compare Channel register here in 0x00-0x03 range.
// <id> tcc_arch_sel_ch
#ifndef CONF_TCC0_SEL_CH
#define CONF_TCC0_SEL_CH 0x1
#endif
/* Caculate pwm ccx register value based on WAVE_PER_VAL and Waveform Duty Value */
#if CONF_TCC0_PRESCALER < TCC_CTRLA_PRESCALER_DIV64_Val
#define CONF_TCC0_PER_REG \
((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1000000 / (1 << CONF_TCC0_PRESCALER) - 1))
#define CONF_TCC0_CCX_REG ((uint32_t)(((double)(double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV64_Val
#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 64000000 - 1))
#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV256_Val
#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 256000000 - 1))
#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
#elif CONF_TCC0_PRESCALER == TCC_CTRLA_PRESCALER_DIV1024_Val
#define CONF_TCC0_PER_REG ((uint32_t)(((double)CONF_TCC0_WAVE_PER_VAL * CONF_GCLK_TCC0_FREQUENCY) / 1024000000 - 1))
#define CONF_TCC0_CCX_REG ((uint32_t)(((double)CONF_TCC0_PER_REG * CONF_TCC0_WAVE_DUTY_VAL) / 1000))
#endif
// </h>
// <h> Advanced settings
/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL A register.
* May be used by other abstractions based on TC. */
//#define CONF_TCC0_RESOLUTION TCC_CTRLA_RESOLUTION_NONE_Val
// <q> Run in standby
// <i> Indicates whether the TCC0 will continue running in standby sleep mode or not
// <id> tcc_arch_runstdby
#ifndef CONF_TCC0_RUNSTDBY
#define CONF_TCC0_RUNSTDBY 0
#endif
// <y> TCC0 Prescaler and Counter Synchronization Selection
// <TCC_CTRLA_PRESCSYNC_GCLK_Val"> Reload or reset counter on next GCLK
// <TCC_CTRLA_PRESCSYNC_PRESC_Val"> Reload or reset counter on next prescaler clock
// <TCC_CTRLA_PRESCSYNC_RESYNC_Val"> Reload or reset counter on next GCLK and reset prescaler counter
// <i> These bits select if on retrigger event, the Counter should be cleared or reloaded on the next GCLK_TCCx clock or on the next prescaled GCLK_TCCx clock.
// <id> tcc_arch_prescsync
#ifndef CONF_TCC0_PRESCSYNC
#define CONF_TCC0_PRESCSYNC TCC_CTRLA_PRESCSYNC_GCLK_Val
#endif
// <y> TCC0 Waveform Generation Selection
// <TCC_WAVE_WAVEGEN_NPWM_Val"> Single-slope PWM
// <TCC_WAVE_WAVEGEN_DSCRITICAL_Val"> Dual-slope, critical interrupt/event at ZERO (DSCRITICAL)
// <TCC_WAVE_WAVEGEN_DSBOTTOM_Val"> Dual-slope, interrupt/event at ZERO (DSBOTTOM)
// <TCC_WAVE_WAVEGEN_DSBOTH_Val"> Dual-slope, interrupt/event at Top and ZERO (DSBOTH)
// <TCC_WAVE_WAVEGEN_DSTOP_Val"> Dual-slope, interrupt/event at Top (DSTOP)
// <id> tcc_arch_wavegen
#ifndef CONF_TCC0_WAVEGEN
#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_NPWM_Val
#endif
// <q> TCC0 Auto Lock
// <i> Indicates whether the TCC0 Auto Lock is enabled or not
// <id> tcc_arch_alock
#ifndef CONF_TCC0_ALOCK
#define CONF_TCC0_ALOCK 0
#endif
// <q> TCC0 Capture Channel 0 Enable
// <i> Indicates whether the TCC0 Capture Channel 0 is enabled or not
// <id> tcc_arch_cpten0
#ifndef CONF_TCC0_CPTEN0
#define CONF_TCC0_CPTEN0 0
#endif
// <q> TCC0 Capture Channel 1 Enable
// <i> Indicates whether the TCC0 Capture Channel 1 is enabled or not
// <id> tcc_arch_cpten1
#ifndef CONF_TCC0_CPTEN1
#define CONF_TCC0_CPTEN1 0
#endif
// <q> TCC0 Capture Channel 2 Enable
// <i> Indicates whether the TCC0 Capture Channel 2 is enabled or not
// <id> tcc_arch_cpten2
#ifndef CONF_TCC0_CPTEN2
#define CONF_TCC0_CPTEN2 0
#endif
// <q> TCC0 Capture Channel 3 Enable
// <i> Indicates whether the TCC0 Capture Channel 3 is enabled or not
// <id> tcc_arch_cpten3
#ifndef CONF_TCC0_CPTEN3
#define CONF_TCC0_CPTEN3 0
#endif
// <hidden>
// <q> TCC0 Capture Channel 4 Enable
// <i> Indicates whether the TCC0 Capture Channel 4 is enabled or not
// <id> tcc_arch_cpten4
#ifndef CONF_TCC0_CPTEN4
#define CONF_TCC0_CPTEN4 0
#endif
// </hidden>
// <hidden>
// <q> TCC0 Capture Channel 5 Enable
// <i> Indicates whether the TCC0 Capture Channel 5 is enabled or not
// <id> tcc_arch_cpten5
#ifndef CONF_TCC0_CPTEN5
#define CONF_TCC0_CPTEN5 0
#endif
// </hidden>
// <hidden>
// <q> TCC0 Capture Channel 6 Enable
// <i> Indicates whether the TCC0 Capture Channel 6 is enabled or not
// <id> tcc_arch_cpten6
#ifndef CONF_TCC0_CPTEN6
#define CONF_TCC0_CPTEN6 0
#endif
// </hidden>
// <hidden>
// <q> TCC0 Capture Channel 7 Enable
// <i> Indicates whether the TCC0 Capture Channel 7 is enabled or not
// <id> tcc_arch_cpten7
#ifndef CONF_TCC0_CPTEN7
#define CONF_TCC0_CPTEN7 0
#endif
// </hidden>
// <q> TCC0 Lock update
// <i> Indicates whether the TCC0 Lock update is enabled or not
// <id> tcc_arch_lupd
#ifndef CONF_TCC0_LUPD
#define CONF_TCC0_LUPD 1
#endif
/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of CTRL B register.
* May be used by other abstractions based on TC. */
//#define CONF_TCC0_DIR 0
//#define CONF_TCC0_ONESHOT 0
/* Commented intentionally. No fault control for timers. */
/*#define CONF_TCC0_FAULT_A_SRC TCC_FCTRLA_SRC_DISABLE_Val
#define CONF_TCC0_FAULT_A_KEEP 0
#define CONF_TCC0_FAULT_A_QUAL 0
#define CONF_TCC0_FAULT_A_BLANK TCC_FCTRLA_BLANK_DISABLE_Val
#define CONF_TCC0_FAULT_A_RESTART 0
#define CONF_TCC0_FAULT_A_HALT TCC_FCTRLA_HALT_DISABLE_Val
#define CONF_TCC0_FAULT_A_CHSEL TCC_FCTRLA_CHSEL_CC0_Val
#define CONF_TCC0_FAULT_A_CAPTURE TCC_FCTRLA_CAPTURE_DISABLE_Val
#define CONF_TCC0_FAULT_A_BLACNKPRESC 0
#define CONF_TCC0_FAULT_A_BLANKVAL 0
#define CONF_TCC0_FAULT_A_FILTERVAL 0
#define CONF_TCC0_FAULT_B_SRC TCC_FCTRLB_SRC_DISABLE_Val
#define CONF_TCC0_FAULT_B_KEEP 0
#define CONF_TCC0_FAULT_B_QUAL 0
#define CONF_TCC0_FAULT_B_BLANK TCC_FCTRLB_BLANK_DISABLE_Val
#define CONF_TCC0_FAULT_B_RESTART 0
#define CONF_TCC0_FAULT_B_HALT TCC_FCTRLB_HALT_DISABLE_Val
#define CONF_TCC0_FAULT_B_CHSEL TCC_FCTRLB_CHSEL_CC0_Val
#define CONF_TCC0_FAULT_B_CAPTURE TCC_FCTRLB_CAPTURE_DISABLE_Val
#define CONF_TCC0_FAULT_B_BLACNKPRESC 0
#define CONF_TCC0_FAULT_B_BLANKVAL 0
#define CONF_TCC0_FAULT_B_FILTERVAL 0*/
/* Commented intentionally. No dead-time control for timers. */
/*#define CONF_TCC0_OTMX 0
#define CONF_TCC0_DTIEN0 0
#define CONF_TCC0_DTIEN1 0
#define CONF_TCC0_DTIEN2 0
#define CONF_TCC0_DTIEN3 0
#define CONF_TCC0_DTHS 0*/
/* Commented intentionally. No driver control for timers. */
/*#define CONF_TCC0_NRE0 0
#define CONF_TCC0_NRE1 0
#define CONF_TCC0_NRE2 0
#define CONF_TCC0_NRE3 0
#define CONF_TCC0_NRE4 0
#define CONF_TCC0_NRE5 0
#define CONF_TCC0_NRE6 0
#define CONF_TCC0_NRE7 0
#define CONF_TCC0_NVR0 0
#define CONF_TCC0_NVR1 0
#define CONF_TCC0_NVR2 0
#define CONF_TCC0_NVR3 0
#define CONF_TCC0_NVR4 0
#define CONF_TCC0_NVR5 0
#define CONF_TCC0_NVR6 0
#define CONF_TCC0_NVR7 0
#define CONF_TCC0_INVEN0 0
#define CONF_TCC0_INVEN1 0
#define CONF_TCC0_INVEN2 0
#define CONF_TCC0_INVEN3 0
#define CONF_TCC0_INVEN4 0
#define CONF_TCC0_INVEN5 0
#define CONF_TCC0_INVEN6 0
#define CONF_TCC0_INVEN7 0
#define CONF_TCC0_FILTERVAL0 0
#define CONF_TCC0_FILTERVAL1 0*/
// <q> TCC0 Debug Running Mode
// <i> Indicates whether the TCC0 Debug Running Mode is enabled or not
// <id> tcc_arch_dbgrun
#ifndef CONF_TCC0_DBGRUN
#define CONF_TCC0_DBGRUN 0
#endif
/* Commented intentionally. Timer uses fixed value of the following bit(s)/bitfield(s) of Debug Control register.
* May be used by other abstractions based on TC. */
//#define CONF_TCC0_FDDBD 0
// <e> Event control
// <id> timer_event_control
#ifndef CONF_TCC0_EVENT_CONTROL_ENABLE
#define CONF_TCC0_EVENT_CONTROL_ENABLE 0
#endif
// <q> Match or Capture Channel 0 Event Output
// <i> This bit indicates whether match/capture event on channel 0 is enabled and will be generated
// <id> tcc_arch_mceo0
#ifndef CONF_TCC0_MCEO0
#define CONF_TCC0_MCEO0 0
#endif
// <q> Match or Capture Channel 0 Event Input
// <i> This bit indicates whether match/capture 0 incoming event is enabled
// <id> tcc_arch_mcei0
#ifndef CONF_TCC0_MCEI0
#define CONF_TCC0_MCEI0 0
#endif
// <q> Match or Capture Channel 1 Event Output
// <i> This bit indicates whether match/capture event on channel 1 is enabled and will be generated
// <id> tcc_arch_mceo1
#ifndef CONF_TCC0_MCEO1
#define CONF_TCC0_MCEO1 0
#endif
// <q> Match or Capture Channel 1 Event Input
// <i> This bit indicates whether match/capture 1 incoming event is enabled
// <id> tcc_arch_mcei1
#ifndef CONF_TCC0_MCEI1
#define CONF_TCC0_MCEI1 0
#endif
// <q> Match or Capture Channel 2 Event Output
// <i> This bit indicates whether match/capture event on channel 2 is enabled and will be generated
// <id> tcc_arch_mceo2
#ifndef CONF_TCC0_MCEO2
#define CONF_TCC0_MCEO2 0
#endif
// <q> Match or Capture Channel 2 Event Input
// <i> This bit indicates whether match/capture 2 incoming event is enabled
// <id> tcc_arch_mcei2
#ifndef CONF_TCC0_MCEI2
#define CONF_TCC0_MCEI2 0
#endif
// <q> Match or Capture Channel 3 Event Output
// <i> This bit indicates whether match/capture event on channel 3 is enabled and will be generated
// <id> tcc_arch_mceo3
#ifndef CONF_TCC0_MCEO3
#define CONF_TCC0_MCEO3 0
#endif
// <q> Match or Capture Channel 3 Event Input
// <i> This bit indicates whether match/capture 3 incoming event is enabled
// <id> tcc_arch_mcei3
#ifndef CONF_TCC0_MCEI3
#define CONF_TCC0_MCEI3 0
#endif
// <q> Timer/Counter Event Input 0
// <i> This bit is used to enable input event 0 to the TCC
// <id> tcc_arch_tcei0
#ifndef CONF_TCC0_TCEI0
#define CONF_TCC0_TCEI0 0
#endif
// <q> Timer/Counter Event Input 0 Invert
// <i> This bit inverts the event 0 input
// <id> tcc_arch_tceinv0
#ifndef CONF_TCC0_TCINV0
#define CONF_TCC0_TCINV0 0
#endif
// <q> Timer/Counter Event Input 1
// <i> This bit is used to enable input event 1 to the TCC
// <id> tcc_arch_tcei1
#ifndef CONF_TCC0_TCEI1
#define CONF_TCC0_TCEI1 0
#endif
// <q> Timer/Counter Event Input 1 Invert
// <i> This bit inverts the event 1 input
// <id> tcc_arch_tceinv1
#ifndef CONF_TCC0_TCINV1
#define CONF_TCC0_TCINV1 0
#endif
// <q> Timer/Counter Event Output
// <i> This bit is used to enable the counter cycle event.
//<id> tcc_arch_cnteo
#ifndef CONF_TCC0_CNTEO
#define CONF_TCC0_CNTEO 0
#endif
// <q> Re-trigger Event Output
// <i> This bit is used to enable the counter re-trigger event.
//<id> tcc_arch_trgeo
#ifndef CONF_TCC0_TRGEO
#define CONF_TCC0_TRGEO 0
#endif
// <q> Overflow/Underflow Event Output
// <i> This bit is used to enable enable event on overflow/underflow.
//<id> tcc_arch_ovfeo
#ifndef CONF_TCC0_OVFEO
#define CONF_TCC0_OVFEO 0
#endif
// <o> Timer/Counter Interrupt and Event Output Selection
// <0=> An interrupt/event is generated when a new counter cycle starts
// <1=> An interrupt/event is generated when a counter cycle ends
// <2=> An interrupt/event is generated when a counter cycle ends, except for the first and last cycles
// <3=> An interrupt/event is generated when a new counter cycle starts or a counter cycle ends
// <i> These bits define on which part of the counter cycle the counter event output is generated
// <id> tcc_arch_cntsel
#ifndef CONF_TCC0_CNTSEL
#define CONF_TCC0_CNTSEL 0
#endif
// <o> Timer/Counter Event Input 0 Action
// <0=>Event action disabled
// <1=>Start restart or re-trigger on event
// <2=>Count on event
// <3=>Start on event
// <4=>Increment on event
// <5=>Count on active state of asynchronous event
// <6=>Capture overflow times (Max value)
// <7=>Non-recoverable fault
// <i> These bits define the action the TCC performs on TCE0 event input 0
// <id> tcc_arch_evact0
#ifndef CONF_TCC0_EVACT0
#define CONF_TCC0_EVACT0 0
#endif
// <o> Timer/Counter Event Input 1 Action
// <0=>Event action disabled
// <1=>Re-trigger counter on event
// <2=>Direction control
// <3=>Stop counter on event
// <4=>Decrement counter on event
// <5=>Period capture value in CC0 register, pulse width capture value in CC1 register
// <6=>Period capture value in CC1 register, pulse width capture value in CC0 register
// <7=>Non-recoverable fault
// <i> These bits define the action the TCC performs on TCE0 event input 0
// <id> tcc_arch_evact1
#ifndef CONF_TCC0_EVACT1
#define CONF_TCC0_EVACT1 0
#endif
// </e>
/* Commented intentionally. No pattern control for timers. */
/*#define CONF_TCC0_PGE0 0
#define CONF_TCC0_PGE1 0
#define CONF_TCC0_PGE2 0
#define CONF_TCC0_PGE3 0
#define CONF_TCC0_PGE4 0
#define CONF_TCC0_PGE5 0
#define CONF_TCC0_PGE6 0
#define CONF_TCC0_PGE7 0
#define CONF_TCC0_PGV0 0
#define CONF_TCC0_PGV1 0
#define CONF_TCC0_PGV2 0
#define CONF_TCC0_PGV3 0
#define CONF_TCC0_PGV4 0
#define CONF_TCC0_PGV5 0
#define CONF_TCC0_PGV6 0
#define CONF_TCC0_PGV7 0*/
/* Commented intentionally. No pattern waveform control for timers. */
/*#define CONF_TCC0_WAVEGEN TCC_WAVE_WAVEGEN_MFRQ_Val
#define CONF_TCC0_RAMP TCC_WAVE_RAMP_RAMP1_Val
#define CONF_TCC0_CIPEREN 0
#define CONF_TCC0_CICCEN0 0
#define CONF_TCC0_CICCEN1 0
#define CONF_TCC0_CICCEN2 0
#define CONF_TCC0_CICCEN3 0
#define CONF_TCC0_POL0 0
#define CONF_TCC0_POL1 0
#define CONF_TCC0_POL2 0
#define CONF_TCC0_POL3 0
#define CONF_TCC0_POL4 0
#define CONF_TCC0_POL5 0
#define CONF_TCC0_POL6 0
#define CONF_TCC0_POL7 0
#define CONF_TCC0_SWAP0 0
#define CONF_TCC0_SWAP1 0
#define CONF_TCC0_SWAP2 0
#define CONF_TCC0_SWAP3 0*/
//<o> TCC0 Compare and Capture value 0 <0x00-0xFFFFFF>
// <id> tcc_arch_cc0
#ifndef CONF_TCC0_CC0
#define CONF_TCC0_CC0 0x0
#endif
//<o> TCC0 Compare and Capture value 1 <0x00-0xFFFFFF>
// <id> tcc_arch_cc1
#ifndef CONF_TCC0_CC1
#define CONF_TCC0_CC1 0x0
#endif
//<o> TCC0 Compare and Capture value 2 <0x00-0xFFFFFF>
// <id> tcc_arch_cc2
#ifndef CONF_TCC0_CC2
#define CONF_TCC0_CC2 0x0
#endif
//<o> TCC0 Compare and Capture value 3 <0x00-0xFFFFFF>
// <id> tcc_arch_cc3
#ifndef CONF_TCC0_CC3
#define CONF_TCC0_CC3 0x0
#endif
/* Commented intentionally. No pattern control for timers. */
/*#define CONF_TCC0_PATTB_PGEB0 0
#define CONF_TCC0_PATTB_PGEB1 0
#define CONF_TCC0_PATTB_PGEB2 0
#define CONF_TCC0_PATTB_PGEB3 0
#define CONF_TCC0_PATTB_PGEB4 0
#define CONF_TCC0_PATTB_PGEB5 0
#define CONF_TCC0_PATTB_PGEB6 0
#define CONF_TCC0_PATTB_PGEB7 0
#define CONF_TCC0_PATTB_PGVB0 0
#define CONF_TCC0_PATTB_PGVB1 0
#define CONF_TCC0_PATTB_PGVB2 0
#define CONF_TCC0_PATTB_PGVB3 0
#define CONF_TCC0_PATTB_PGVB4 0
#define CONF_TCC0_PATTB_PGVB5 0
#define CONF_TCC0_PATTB_PGVB6 0
#define CONF_TCC0_PATTB_PGVB7 0*/
/* Commented intentionally. No waveform control for timers. */
/*#define CONF_TCC0_WAVEGENB TCC_WAVEB_WAVEGENB_MFRQ_Val
#define CONF_TCC0_RAMPB TCC_WAVE_RAMP_RAMP1_Val
#define CONF_TCC0_CIPERENB 0
#define CONF_TCC0_CICCEN0B 0
#define CONF_TCC0_CICCEN1B 0
#define CONF_TCC0_CICCEN2B 0
#define CONF_TCC0_CICCEN3B 0
#define CONF_TCC0_POL0B 0
#define CONF_TCC0_POL1B 0
#define CONF_TCC0_POL2B 0
#define CONF_TCC0_POL3B 0
#define CONF_TCC0_POL4B 0
#define CONF_TCC0_POL5B 0
#define CONF_TCC0_POL6B 0
#define CONF_TCC0_POL7B 0
#define CONF_TCC0_SWAP0B 0
#define CONF_TCC0_SWAP1B 0
#define CONF_TCC0_SWAP2B 0
#define CONF_TCC0_SWAP3B 0*/
/* Commented intentionally. No buffering for timers. */
/*#define CONF_TCC0_PERB 0
#define CONF_TCC0_CCB0 0
#define CONF_TCC0_CCB1 0
#define CONF_TCC0_CCB2 0
#define CONF_TCC0_CCB3 0*/
// </h>
#define CONF_TCC0_CTRLA \
TCC_CTRLA_PRESCALER(CONF_TCC0_PRESCALER) | (CONF_TCC0_RUNSTDBY << TCC_CTRLA_RUNSTDBY_Pos) \
| TCC_CTRLA_PRESCSYNC(CONF_TCC0_PRESCSYNC) | (CONF_TCC0_CPTEN0 << TCC_CTRLA_CPTEN0_Pos) \
| (CONF_TCC0_CPTEN1 << TCC_CTRLA_CPTEN1_Pos) | (CONF_TCC0_CPTEN2 << TCC_CTRLA_CPTEN2_Pos) \
| (CONF_TCC0_CPTEN3 << TCC_CTRLA_CPTEN3_Pos) | (CONF_TCC0_ALOCK << TCC_CTRLA_ALOCK_Pos)
#define CONF_TCC0_CTRLB (CONF_TCC0_LUPD << TCC_CTRLBSET_LUPD_Pos)
#define CONF_TCC0_DBGCTRL (CONF_TCC0_DBGRUN << TCC_DBGCTRL_DBGRUN_Pos)
#define CONF_TCC0_EVCTRL \
TCC_EVCTRL_CNTSEL(CONF_TCC0_CNTSEL) | (CONF_TCC0_OVFEO << TCC_EVCTRL_OVFEO_Pos) \
| (CONF_TCC0_TRGEO << TCC_EVCTRL_TRGEO_Pos) | (CONF_TCC0_CNTEO << TCC_EVCTRL_CNTEO_Pos) \
| (CONF_TCC0_MCEO0 << TCC_EVCTRL_MCEO0_Pos) | (CONF_TCC0_MCEI0 << TCC_EVCTRL_MCEI0_Pos) \
| (CONF_TCC0_MCEO1 << TCC_EVCTRL_MCEO1_Pos) | (CONF_TCC0_MCEI1 << TCC_EVCTRL_MCEI1_Pos) \
| (CONF_TCC0_MCEO2 << TCC_EVCTRL_MCEO2_Pos) | (CONF_TCC0_MCEI2 << TCC_EVCTRL_MCEI2_Pos) \
| (CONF_TCC0_MCEO3 << TCC_EVCTRL_MCEO3_Pos) | (CONF_TCC0_MCEI3 << TCC_EVCTRL_MCEI3_Pos) \
| (CONF_TCC0_TCEI0 << TCC_EVCTRL_TCEI0_Pos) | (CONF_TCC0_TCEI1 << TCC_EVCTRL_TCEI1_Pos) \
| (CONF_TCC0_TCINV0 << TCC_EVCTRL_TCINV0_Pos) | (CONF_TCC0_TCINV1 << TCC_EVCTRL_TCINV1_Pos) \
| TCC_EVCTRL_EVACT1(CONF_TCC0_EVACT1) | TCC_EVCTRL_EVACT0(CONF_TCC0_EVACT0)
// <<< end of configuration section >>>
#endif // HPL_TCC_CONFIG_H

214
Smol Watch Project/My Project/Config/peripheral_clk_config.h
View file

@ -1,214 +0,0 @@
/* Auto-generated config file peripheral_clk_config.h */
#ifndef PERIPHERAL_CLK_CONFIG_H
#define PERIPHERAL_CLK_CONFIG_H
// <<< Use Configuration Wizard in Context Menu >>>
// <y> ADC Clock Source
// <id> adc_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <i> Select the clock source for ADC.
#ifndef CONF_GCLK_ADC_SRC
#define CONF_GCLK_ADC_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_ADC_FREQUENCY
* \brief ADC's Clock frequency
*/
#ifndef CONF_GCLK_ADC_FREQUENCY
#define CONF_GCLK_ADC_FREQUENCY 4000000
#endif
// <y> EIC Clock Source
// <id> eic_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <i> Select the clock source for EIC.
#ifndef CONF_GCLK_EIC_SRC
#define CONF_GCLK_EIC_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_EIC_FREQUENCY
* \brief EIC's Clock frequency
*/
#ifndef CONF_GCLK_EIC_FREQUENCY
#define CONF_GCLK_EIC_FREQUENCY 32768
#endif
/**
* \def CONF_CPU_FREQUENCY
* \brief CPU's Clock frequency
*/
#ifndef CONF_CPU_FREQUENCY
#define CONF_CPU_FREQUENCY 4000000
#endif
// <y> RTC Clock Source
// <id> rtc_clk_selection
// <RTC_CLOCK_SOURCE"> RTC source
// <i> Select the clock source for RTC.
#ifndef CONF_GCLK_RTC_SRC
#define CONF_GCLK_RTC_SRC RTC_CLOCK_SOURCE
#endif
/**
* \def CONF_GCLK_RTC_FREQUENCY
* \brief RTC's Clock frequency
*/
#ifndef CONF_GCLK_RTC_FREQUENCY
#define CONF_GCLK_RTC_FREQUENCY 1024
#endif
// <y> Core Clock Source
// <id> core_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <i> Select the clock source for CORE.
#ifndef CONF_GCLK_SERCOM1_CORE_SRC
#define CONF_GCLK_SERCOM1_CORE_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
// <y> Slow Clock Source
// <id> slow_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <i> Select the slow clock source.
#ifndef CONF_GCLK_SERCOM1_SLOW_SRC
#define CONF_GCLK_SERCOM1_SLOW_SRC GCLK_PCHCTRL_GEN_GCLK3_Val
#endif
/**
* \def CONF_GCLK_SERCOM1_CORE_FREQUENCY
* \brief SERCOM1's Core Clock frequency
*/
#ifndef CONF_GCLK_SERCOM1_CORE_FREQUENCY
#define CONF_GCLK_SERCOM1_CORE_FREQUENCY 4000000
#endif
/**
* \def CONF_GCLK_SERCOM1_SLOW_FREQUENCY
* \brief SERCOM1's Slow Clock frequency
*/
#ifndef CONF_GCLK_SERCOM1_SLOW_FREQUENCY
#define CONF_GCLK_SERCOM1_SLOW_FREQUENCY 32768
#endif
// <y> TC Clock Source
// <id> tc_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <i> Select the clock source for TC.
#ifndef CONF_GCLK_TC3_SRC
#define CONF_GCLK_TC3_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_TC3_FREQUENCY
* \brief TC3's Clock frequency
*/
#ifndef CONF_GCLK_TC3_FREQUENCY
#define CONF_GCLK_TC3_FREQUENCY 4000000
#endif
// <y> TCC Clock Source
// <id> tcc_gclk_selection
// <GCLK_PCHCTRL_GEN_GCLK0_Val"> Generic clock generator 0
// <GCLK_PCHCTRL_GEN_GCLK1_Val"> Generic clock generator 1
// <GCLK_PCHCTRL_GEN_GCLK2_Val"> Generic clock generator 2
// <GCLK_PCHCTRL_GEN_GCLK3_Val"> Generic clock generator 3
// <GCLK_PCHCTRL_GEN_GCLK4_Val"> Generic clock generator 4
// <i> Select the clock source for TCC.
#ifndef CONF_GCLK_TCC0_SRC
#define CONF_GCLK_TCC0_SRC GCLK_PCHCTRL_GEN_GCLK0_Val
#endif
/**
* \def CONF_GCLK_TCC0_FREQUENCY
* \brief TCC0's Clock frequency
*/
#ifndef CONF_GCLK_TCC0_FREQUENCY
#define CONF_GCLK_TCC0_FREQUENCY 4000000
#endif
#include <hpl_osc32kctrl_config.h>
// <y> SLCD Clock Source
// <id> slcd_clk_selection
// <SLCD_CLOCK_SOURCE"> SLCD source
// <i> Select the clock source for SLCD.
#ifndef CONF_GCLK_SLCD_SRC
#define CONF_GCLK_SLCD_SRC SLCD_CLOCK_SOURCE
#endif
/**
* \def CONF_GCLK_SLCD_FREQUENCY
* \brief SLCD's Clock frequency
*/
#ifndef CONF_GCLK_SLCD_FREQUENCY
#define CONF_GCLK_SLCD_FREQUENCY 32768
#endif
#ifndef SLCD_FRAME_FREQUENCY
#define SLCD_FRAME_FREQUENCY \
(CONF_GCLK_SLCD_FREQUENCY \
/ (((CONF_SLCD_PRESC + 1) * 16) * (CONF_SLCD_CKDIV + 1) \
* ((CONF_SLCD_COM_NUM == 4) ? 6 : ((CONF_SLCD_COM_NUM == 5) ? 8 : (CONF_SLCD_COM_NUM + 1)))))
#endif
// <<< end of configuration section >>>
#endif // PERIPHERAL_CLK_CONFIG_H

628
Smol Watch Project/My Project/Debug/Makefile
View file

@ -1,628 +0,0 @@
################################################################################
# Automatically-generated file. Do not edit!
################################################################################
SHELL := cmd.exe
RM := rm -rf
USER_OBJS :=
LIBS :=
PROJ :=
O_SRCS :=
C_SRCS :=
S_SRCS :=
S_UPPER_SRCS :=
OBJ_SRCS :=
ASM_SRCS :=
PREPROCESSING_SRCS :=
OBJS :=
OBJS_AS_ARGS :=
C_DEPS :=
C_DEPS_AS_ARGS :=
EXECUTABLES :=
OUTPUT_FILE_PATH :=
OUTPUT_FILE_PATH_AS_ARGS :=
AVR_APP_PATH :=$$$AVR_APP_PATH$$$
QUOTE := "
ADDITIONAL_DEPENDENCIES:=
OUTPUT_FILE_DEP:=
LIB_DEP:=
LINKER_SCRIPT_DEP:=
# Every subdirectory with source files must be described here
SUBDIRS := \
../Config/ \
../Device_Startup/ \
../examples/ \
../hal/ \
../hal/documentation/ \
../hal/include/ \
../hal/src/ \
../hal/utils/ \
../hal/utils/include/ \
../hal/utils/src/ \
../hpl/ \
../hpl/adc/ \
../hpl/core/ \
../hpl/dmac/ \
../hpl/doc_lite/ \
../hpl/eic/ \
../hpl/gclk/ \
../hpl/mclk/ \
../hpl/osc32kctrl/ \
../hpl/oscctrl/ \
../hpl/pm/ \
../hpl/port/ \
../hpl/rtc/ \
../hpl/sercom/ \
../hpl/slcd/ \
../hpl/systick/ \
../hpl/tcc/ \
../hpl/tc/ \
../hri/ \
../watch-library
# Add inputs and outputs from these tool invocations to the build variables
C_SRCS += \
../atmel_start.c \
../Device_Startup/startup_saml22.c \
../Device_Startup/system_saml22.c \
../driver_init.c \
../examples/driver_examples.c \
../hal/src/hal_adc_sync.c \
../hal/src/hal_atomic.c \
../hal/src/hal_calendar.c \
../hal/src/hal_delay.c \
../hal/src/hal_ext_irq.c \
../hal/src/hal_gpio.c \
../hal/src/hal_i2c_m_sync.c \
../hal/src/hal_init.c \
../hal/src/hal_io.c \
../hal/src/hal_pwm.c \
../hal/src/hal_slcd_sync.c \
../hal/src/hal_sleep.c \
../hal/utils/src/utils_assert.c \
../hal/utils/src/utils_event.c \
../hal/utils/src/utils_list.c \
../hal/utils/src/utils_syscalls.c \
../hpl/adc/hpl_adc.c \
../hpl/core/hpl_core_m0plus_base.c \
../hpl/core/hpl_init.c \
../hpl/dmac/hpl_dmac.c \
../hpl/eic/hpl_eic.c \
../hpl/gclk/hpl_gclk.c \
../hpl/mclk/hpl_mclk.c \
../hpl/osc32kctrl/hpl_osc32kctrl.c \
../hpl/oscctrl/hpl_oscctrl.c \
../hpl/pm/hpl_pm.c \
../hpl/rtc/hpl_rtc.c \
../hpl/sercom/hpl_sercom.c \
../hpl/slcd/hpl_slcd.c \
../hpl/systick/hpl_systick.c \
../hpl/tcc/hpl_tcc.c \
../hpl/tc/tc_lite.c \
../mars_clock.c \
../main.c \
../watch-library/watch.c
PREPROCESSING_SRCS +=
ASM_SRCS +=
OBJS += \
atmel_start.o \
Device_Startup/startup_saml22.o \
Device_Startup/system_saml22.o \
driver_init.o \
examples/driver_examples.o \
hal/src/hal_adc_sync.o \
hal/src/hal_atomic.o \
hal/src/hal_calendar.o \
hal/src/hal_delay.o \
hal/src/hal_ext_irq.o \
hal/src/hal_gpio.o \
hal/src/hal_i2c_m_sync.o \
hal/src/hal_init.o \
hal/src/hal_io.o \
hal/src/hal_pwm.o \
hal/src/hal_slcd_sync.o \
hal/src/hal_sleep.o \
hal/utils/src/utils_assert.o \
hal/utils/src/utils_event.o \
hal/utils/src/utils_list.o \
hal/utils/src/utils_syscalls.o \
hpl/adc/hpl_adc.o \
hpl/core/hpl_core_m0plus_base.o \
hpl/core/hpl_init.o \
hpl/dmac/hpl_dmac.o \
hpl/eic/hpl_eic.o \
hpl/gclk/hpl_gclk.o \
hpl/mclk/hpl_mclk.o \
hpl/osc32kctrl/hpl_osc32kctrl.o \
hpl/oscctrl/hpl_oscctrl.o \
hpl/pm/hpl_pm.o \
hpl/rtc/hpl_rtc.o \
hpl/sercom/hpl_sercom.o \
hpl/slcd/hpl_slcd.o \
hpl/systick/hpl_systick.o \
hpl/tcc/hpl_tcc.o \
hpl/tc/tc_lite.o \
mars_clock.o \
main.o \
watch-library/watch.o
OBJS_AS_ARGS += \
atmel_start.o \
Device_Startup/startup_saml22.o \
Device_Startup/system_saml22.o \
driver_init.o \
examples/driver_examples.o \
hal/src/hal_adc_sync.o \
hal/src/hal_atomic.o \
hal/src/hal_calendar.o \
hal/src/hal_delay.o \
hal/src/hal_ext_irq.o \
hal/src/hal_gpio.o \
hal/src/hal_i2c_m_sync.o \
hal/src/hal_init.o \
hal/src/hal_io.o \
hal/src/hal_pwm.o \
hal/src/hal_slcd_sync.o \
hal/src/hal_sleep.o \
hal/utils/src/utils_assert.o \
hal/utils/src/utils_event.o \
hal/utils/src/utils_list.o \
hal/utils/src/utils_syscalls.o \
hpl/adc/hpl_adc.o \
hpl/core/hpl_core_m0plus_base.o \
hpl/core/hpl_init.o \
hpl/dmac/hpl_dmac.o \
hpl/eic/hpl_eic.o \
hpl/gclk/hpl_gclk.o \
hpl/mclk/hpl_mclk.o \
hpl/osc32kctrl/hpl_osc32kctrl.o \
hpl/oscctrl/hpl_oscctrl.o \
hpl/pm/hpl_pm.o \
hpl/rtc/hpl_rtc.o \
hpl/sercom/hpl_sercom.o \
hpl/slcd/hpl_slcd.o \
hpl/systick/hpl_systick.o \
hpl/tcc/hpl_tcc.o \
hpl/tc/tc_lite.o \
mars_clock.o \
main.o \
watch-library/watch.o
C_DEPS += \
atmel_start.d \
Device_Startup/startup_saml22.d \
Device_Startup/system_saml22.d \
driver_init.d \
examples/driver_examples.d \
hal/src/hal_adc_sync.d \
hal/src/hal_atomic.d \
hal/src/hal_calendar.d \
hal/src/hal_delay.d \
hal/src/hal_ext_irq.d \
hal/src/hal_gpio.d \
hal/src/hal_i2c_m_sync.d \
hal/src/hal_init.d \
hal/src/hal_io.d \
hal/src/hal_pwm.d \
hal/src/hal_slcd_sync.d \
hal/src/hal_sleep.d \
hal/utils/src/utils_assert.d \
hal/utils/src/utils_event.d \
hal/utils/src/utils_list.d \
hal/utils/src/utils_syscalls.d \
hpl/adc/hpl_adc.d \
hpl/core/hpl_core_m0plus_base.d \
hpl/core/hpl_init.d \
hpl/dmac/hpl_dmac.d \
hpl/eic/hpl_eic.d \
hpl/gclk/hpl_gclk.d \
hpl/mclk/hpl_mclk.d \
hpl/osc32kctrl/hpl_osc32kctrl.d \
hpl/oscctrl/hpl_oscctrl.d \
hpl/pm/hpl_pm.d \
hpl/rtc/hpl_rtc.d \
hpl/sercom/hpl_sercom.d \
hpl/slcd/hpl_slcd.d \
hpl/systick/hpl_systick.d \
hpl/tcc/hpl_tcc.d \
hpl/tc/tc_lite.d \
mars_clock.d \
main.d \
watch-library/watch.d
C_DEPS_AS_ARGS += \
atmel_start.d \
Device_Startup/startup_saml22.d \
Device_Startup/system_saml22.d \
driver_init.d \
examples/driver_examples.d \
hal/src/hal_adc_sync.d \
hal/src/hal_atomic.d \
hal/src/hal_calendar.d \
hal/src/hal_delay.d \
hal/src/hal_ext_irq.d \
hal/src/hal_gpio.d \
hal/src/hal_i2c_m_sync.d \
hal/src/hal_init.d \
hal/src/hal_io.d \
hal/src/hal_pwm.d \
hal/src/hal_slcd_sync.d \
hal/src/hal_sleep.d \
hal/utils/src/utils_assert.d \
hal/utils/src/utils_event.d \
hal/utils/src/utils_list.d \
hal/utils/src/utils_syscalls.d \
hpl/adc/hpl_adc.d \
hpl/core/hpl_core_m0plus_base.d \
hpl/core/hpl_init.d \
hpl/dmac/hpl_dmac.d \
hpl/eic/hpl_eic.d \
hpl/gclk/hpl_gclk.d \
hpl/mclk/hpl_mclk.d \
hpl/osc32kctrl/hpl_osc32kctrl.d \
hpl/oscctrl/hpl_oscctrl.d \
hpl/pm/hpl_pm.d \
hpl/rtc/hpl_rtc.d \
hpl/sercom/hpl_sercom.d \
hpl/slcd/hpl_slcd.d \
hpl/systick/hpl_systick.d \
hpl/tcc/hpl_tcc.d \
hpl/tc/tc_lite.d \
mars_clock.d \
main.d \
watch-library/watch.d
OUTPUT_FILE_PATH +=My\ Project.elf
OUTPUT_FILE_PATH_AS_ARGS +="My Project.elf"
ADDITIONAL_DEPENDENCIES:=
OUTPUT_FILE_DEP:= ./makedep.mk
LIB_DEP+=
LINKER_SCRIPT_DEP+= \
../Device_Startup/saml22j18a_flash.ld \
../Device_Startup/saml22j18a_sram.ld
# AVR32/GNU C Compiler
./atmel_start.o: .././atmel_start.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
Device_Startup/startup_saml22.o: ../Device_Startup/startup_saml22.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
Device_Startup/system_saml22.o: ../Device_Startup/system_saml22.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
./driver_init.o: .././driver_init.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
examples/driver_examples.o: ../examples/driver_examples.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/src/hal_adc_sync.o: ../hal/src/hal_adc_sync.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/src/hal_atomic.o: ../hal/src/hal_atomic.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/src/hal_calendar.o: ../hal/src/hal_calendar.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/src/hal_delay.o: ../hal/src/hal_delay.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/src/hal_ext_irq.o: ../hal/src/hal_ext_irq.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/src/hal_gpio.o: ../hal/src/hal_gpio.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/src/hal_i2c_m_sync.o: ../hal/src/hal_i2c_m_sync.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/src/hal_init.o: ../hal/src/hal_init.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/src/hal_io.o: ../hal/src/hal_io.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/src/hal_pwm.o: ../hal/src/hal_pwm.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/src/hal_slcd_sync.o: ../hal/src/hal_slcd_sync.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/src/hal_sleep.o: ../hal/src/hal_sleep.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/utils/src/utils_assert.o: ../hal/utils/src/utils_assert.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/utils/src/utils_event.o: ../hal/utils/src/utils_event.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/utils/src/utils_list.o: ../hal/utils/src/utils_list.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hal/utils/src/utils_syscalls.o: ../hal/utils/src/utils_syscalls.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/adc/hpl_adc.o: ../hpl/adc/hpl_adc.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/core/hpl_core_m0plus_base.o: ../hpl/core/hpl_core_m0plus_base.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/core/hpl_init.o: ../hpl/core/hpl_init.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/dmac/hpl_dmac.o: ../hpl/dmac/hpl_dmac.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/eic/hpl_eic.o: ../hpl/eic/hpl_eic.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/gclk/hpl_gclk.o: ../hpl/gclk/hpl_gclk.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/mclk/hpl_mclk.o: ../hpl/mclk/hpl_mclk.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/osc32kctrl/hpl_osc32kctrl.o: ../hpl/osc32kctrl/hpl_osc32kctrl.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/oscctrl/hpl_oscctrl.o: ../hpl/oscctrl/hpl_oscctrl.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/pm/hpl_pm.o: ../hpl/pm/hpl_pm.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/rtc/hpl_rtc.o: ../hpl/rtc/hpl_rtc.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/sercom/hpl_sercom.o: ../hpl/sercom/hpl_sercom.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/slcd/hpl_slcd.o: ../hpl/slcd/hpl_slcd.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/systick/hpl_systick.o: ../hpl/systick/hpl_systick.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/tcc/hpl_tcc.o: ../hpl/tcc/hpl_tcc.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
hpl/tc/tc_lite.o: ../hpl/tc/tc_lite.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
./mars_clock.o: .././mars_clock.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
./main.o: .././main.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
watch-library/watch.o: ../watch-library/watch.c
@echo Building file: $<
@echo Invoking: ARM/GNU C Compiler : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -x c -mthumb -D__SAML22J18A__ -DDEBUG -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include" -I"../Config" -I".." -I"../examples" -I"../hal/include" -I"../hal/utils/include" -I"../hpl/adc" -I"../hpl/core" -I"../hpl/dmac" -I"../hpl/eic" -I"../hpl/gclk" -I"../hpl/mclk" -I"../hpl/osc32kctrl" -I"../hpl/oscctrl" -I"../hpl/pm" -I"../hpl/port" -I"../hpl/rtc" -I"../hpl/sercom" -I"../hpl/slcd" -I"../hpl/systick" -I"../hpl/tc" -I"../hpl/tcc" -I"../hri" -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include" -Og -ffunction-sections -mlong-calls -g3 -Wall -mcpu=cortex-m0plus -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)" -o "$@" "$<"
@echo Finished building: $<
# AVR32/GNU Preprocessing Assembler
# AVR32/GNU Assembler
ifneq ($(MAKECMDGOALS),clean)
ifneq ($(strip $(C_DEPS)),)
-include $(C_DEPS)
endif
endif
# Add inputs and outputs from these tool invocations to the build variables
# All Target
all: $(OUTPUT_FILE_PATH) $(ADDITIONAL_DEPENDENCIES)
$(OUTPUT_FILE_PATH): $(OBJS) $(USER_OBJS) $(OUTPUT_FILE_DEP) $(LIB_DEP) $(LINKER_SCRIPT_DEP)
@echo Building target: $@
@echo Invoking: ARM/GNU Linker : 6.3.1
$(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-gcc.exe$(QUOTE) -o$(OUTPUT_FILE_PATH_AS_ARGS) $(OBJS_AS_ARGS) $(USER_OBJS) $(LIBS) -mthumb -Wl,-Map="My Project.map" --specs=nano.specs -Wl,--start-group -lm -Wl,--end-group -L"..\\Device_Startup" -Wl,--gc-sections -mcpu=cortex-m0plus -Tsaml22j18a_flash.ld
@echo Finished building target: $@
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O binary "My Project.elf" "My Project.bin"
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O ihex -R .eeprom -R .fuse -R .lock -R .signature "My Project.elf" "My Project.hex"
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -j .eeprom --set-section-flags=.eeprom=alloc,load --change-section-lma .eeprom=0 --no-change-warnings -O binary "My Project.elf" "My Project.eep" || exit 0
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objdump.exe" -h -S "My Project.elf" > "My Project.lss"
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-objcopy.exe" -O srec -R .eeprom -R .fuse -R .lock -R .signature "My Project.elf" "My Project.srec"
"C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\arm\arm-gnu-toolchain\bin\arm-none-eabi-size.exe" "My Project.elf"
# Other Targets
clean:
-$(RM) $(OBJS_AS_ARGS) $(EXECUTABLES)
-$(RM) $(C_DEPS_AS_ARGS)
rm -rf "My Project.elf" "My Project.a" "My Project.hex" "My Project.bin" "My Project.lss" "My Project.eep" "My Project.map" "My Project.srec"

0
Smol Watch Project/My Project/Debug/My Project.eep
View file

84
Smol Watch Project/My Project/Debug/makedep.mk
View file

@ -1,84 +0,0 @@
################################################################################
# Automatically-generated file. Do not edit or delete the file
################################################################################
atmel_start.c
Device_Startup\startup_saml22.c
Device_Startup\system_saml22.c
driver_init.c
examples\driver_examples.c
hal\src\hal_adc_sync.c
hal\src\hal_atomic.c
hal\src\hal_calendar.c
hal\src\hal_delay.c
hal\src\hal_ext_irq.c
hal\src\hal_gpio.c
hal\src\hal_i2c_m_sync.c
hal\src\hal_init.c
hal\src\hal_io.c
hal\src\hal_pwm.c
hal\src\hal_slcd_sync.c
hal\src\hal_sleep.c
hal\utils\src\utils_assert.c
hal\utils\src\utils_event.c
hal\utils\src\utils_list.c
hal\utils\src\utils_syscalls.c
hpl\adc\hpl_adc.c
hpl\core\hpl_core_m0plus_base.c
hpl\core\hpl_init.c
hpl\dmac\hpl_dmac.c
hpl\eic\hpl_eic.c
hpl\gclk\hpl_gclk.c
hpl\mclk\hpl_mclk.c
hpl\osc32kctrl\hpl_osc32kctrl.c
hpl\oscctrl\hpl_oscctrl.c
hpl\pm\hpl_pm.c
hpl\rtc\hpl_rtc.c
hpl\sercom\hpl_sercom.c
hpl\slcd\hpl_slcd.c
hpl\systick\hpl_systick.c
hpl\tcc\hpl_tcc.c
hpl\tc\tc_lite.c
mars_clock.c
main.c
watch-library\watch.c

475
Smol Watch Project/My Project/Default.xml
View file

@ -1,475 +0,0 @@
<?xml version="1.0" encoding="utf-8"?>
<Configurations xmlns:i="http://www.w3.org/2001/XMLSchema-instance" z:Id="i1" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/" xmlns="DefaultValues">
<Configurations>
<Configuration z:Id="i2">
<Compiler_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
<d4p1:KeyValueOfstringstring>
<d4p1:Key>DebugLevel</d4p1:Key>
<d4p1:Value>None</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>IncludePaths</d4p1:Key>
<d4p1:Value>NDEBUG</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>MiscellaneousSettings</d4p1:Key>
<d4p1:Value>-std=gnu99</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>OptimizationLevel</d4p1:Key>
<d4p1:Value>Optimize for size (-Os)</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>SymbolDefines</d4p1:Key>
<d4p1:Value>NDEBUG</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>SymbolUndefines</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>Verbose</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>WarningsAsErrors</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.general.CLanguageExp</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.general.ChangeDefaultCharTypeUnsigned</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.general.ChangeDefaultBitFieldUnsigned</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.general.processormode</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.preprocessor.DoNotSearchSystemDirectories</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.preprocessor.PreprocessOnly</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.symbols.Default</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.directories.DefaultIncludePath</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.OtherFlags</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.PrepareDataForGarbageCollection</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.EnableFastMath</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.GeneratePositionIndependentCode</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.EnableLongCalls</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.OtherDebuggingFlags</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.GenerateGprofInformation</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.GenerateProfInformation</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.warnings.AllWarnings</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.warnings.ExtraWarnings</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.warnings.Undefined</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.warnings.CheckSyntaxOnly</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.warnings.Pedantic</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.warnings.PedanticWarningsAsErrors</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.warnings.InhibitAllWarnings</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.miscellaneous.Device</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.miscellaneous.CompileOnly</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.miscellaneous.SupportAnsiPrograms</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.miscellaneous.MakeFileDependent</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
</Compiler_dictionary>
<Linker_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
<d4p1:KeyValueOfstringstring>
<d4p1:Key>Libraries</d4p1:Key>
<d4p1:Value>libm</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>LibrarySearchPath</d4p1:Key>
<d4p1:Value>$(ProjectDir)\Device_Startup</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>MiscellaneousSettings</d4p1:Key>
<d4p1:Value>-Tsaml22j18a_flash.ld</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.DoNotUseStandardStartFiles</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.DoNotUseDefaultLibraries</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.NoStartupOrDefaultLibs</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.OmitAllSymbolInformation</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.NoSharedLibraries</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.GenerateMAPFile</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.UseNewlibNano</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.AdditionalSpecs</d4p1:Key>
<d4p1:Value>None</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.optimization.GarbageCollectUnusedSections</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.optimization.EnableFastMath</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.optimization.GeneratePositionIndependentCode</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.memorysettings.Flash</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.memorysettings.Sram</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.memorysettings.ExternalRAM</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.miscellaneous.OtherOptions</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.miscellaneous.OtherObjects</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
</Linker_dictionary>
<Name>Release</Name>
</Configuration>
<Configuration z:Id="i3">
<Compiler_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
<d4p1:KeyValueOfstringstring>
<d4p1:Key>DebugLevel</d4p1:Key>
<d4p1:Value>Maximum (-g3)</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>IncludePaths</d4p1:Key>
<d4p1:Value>DEBUG</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>MiscellaneousSettings</d4p1:Key>
<d4p1:Value>-std=gnu99</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>OptimizationLevel</d4p1:Key>
<d4p1:Value>Optimize debugging experience (-Og)</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>SymbolDefines</d4p1:Key>
<d4p1:Value>DEBUG</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>SymbolUndefines</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>Verbose</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>WarningsAsErrors</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.general.CLanguageExp</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.general.ChangeDefaultCharTypeUnsigned</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.general.ChangeDefaultBitFieldUnsigned</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.general.processormode</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.preprocessor.DoNotSearchSystemDirectories</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.preprocessor.PreprocessOnly</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.symbols.Default</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.directories.DefaultIncludePath</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.OtherFlags</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.PrepareFunctionsForGarbageCollection</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.PrepareDataForGarbageCollection</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.EnableFastMath</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.GeneratePositionIndependentCode</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.EnableLongCalls</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.OtherDebuggingFlags</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.GenerateGprofInformation</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.optimization.GenerateProfInformation</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.warnings.AllWarnings</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.warnings.ExtraWarnings</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.warnings.Undefined</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.warnings.CheckSyntaxOnly</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.warnings.Pedantic</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.warnings.PedanticWarningsAsErrors</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.warnings.InhibitAllWarnings</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.miscellaneous.Device</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.miscellaneous.CompileOnly</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.miscellaneous.SupportAnsiPrograms</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.compiler.miscellaneous.MakeFileDependent</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
</Compiler_dictionary>
<Linker_dictionary xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
<d4p1:KeyValueOfstringstring>
<d4p1:Key>Libraries</d4p1:Key>
<d4p1:Value>libm</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>LibrarySearchPath</d4p1:Key>
<d4p1:Value>$(ProjectDir)\Device_Startup</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>MiscellaneousSettings</d4p1:Key>
<d4p1:Value>-Tsaml22j18a_flash.ld</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.DoNotUseStandardStartFiles</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.DoNotUseDefaultLibraries</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.NoStartupOrDefaultLibs</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.OmitAllSymbolInformation</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.NoSharedLibraries</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.GenerateMAPFile</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.UseNewlibNano</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.general.AdditionalSpecs</d4p1:Key>
<d4p1:Value>None</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.optimization.GarbageCollectUnusedSections</d4p1:Key>
<d4p1:Value>True</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.optimization.EnableUnsafeMatchOptimizations</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.optimization.EnableFastMath</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.optimization.GeneratePositionIndependentCode</d4p1:Key>
<d4p1:Value>False</d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.memorysettings.Flash</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.memorysettings.Sram</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.memorysettings.ExternalRAM</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.miscellaneous.OtherOptions</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
<d4p1:KeyValueOfstringstring>
<d4p1:Key>armgcc.linker.miscellaneous.OtherObjects</d4p1:Key>
<d4p1:Value></d4p1:Value>
</d4p1:KeyValueOfstringstring>
</Linker_dictionary>
<Name>Debug</Name>
</Configuration>
</Configurations>
</Configurations>

143
Smol Watch Project/My Project/Device_Startup/saml22j18a_flash.ld
View file

@ -1,143 +0,0 @@
/**
* \file
*
* \brief Linker script for running in internal FLASH on the SAML22J18A
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

142
Smol Watch Project/My Project/Device_Startup/saml22j18a_sram.ld
View file

@ -1,142 +0,0 @@
/**
* \file
*
* \brief Linker script for running in internal SRAM on the SAML22J18A
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
/* Memory Spaces Definitions */
MEMORY
{
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000
}
/* The stack size used by the application. NOTE: you need to adjust according to your application. */
STACK_SIZE = DEFINED(STACK_SIZE) ? STACK_SIZE : DEFINED(__stack_size__) ? __stack_size__ : 0x2000;
/* Section Definitions */
SECTIONS
{
.text :
{
. = ALIGN(4);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(4);
KEEP(*(.init))
. = ALIGN(4);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(4);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(4);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(4);
KEEP(*(.fini))
. = ALIGN(4);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(4);
_efixed = .; /* End of text section */
} > ram
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > ram
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(4);
_etext = .;
.relocate : AT (_etext)
{
. = ALIGN(4);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(4);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(4);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(4);
_ebss = . ;
_ezero = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
. = ALIGN(4);
_end = . ;
}

225
Smol Watch Project/My Project/Device_Startup/startup_saml22.c
View file

@ -1,225 +0,0 @@
/**
* \file
*
* \brief gcc starttup file for SAML22
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#include "saml22.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M0+ core handlers */
void NonMaskableInt_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVCall_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void SYSTEM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* MCLK, OSC32KCTRL, OSCCTRL, PAC, PM, SUPC, TAL */
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void FREQM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef ID_USB
void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef ID_SERCOM3
void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_SERCOM4
void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_SERCOM5
void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef ID_PTC
void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void SLCD_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef ID_AES
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_TRNG
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
.pvStack = (void*) (&_estack),
.pfnReset_Handler = (void*) Reset_Handler,
.pfnNonMaskableInt_Handler = (void*) NonMaskableInt_Handler,
.pfnHardFault_Handler = (void*) HardFault_Handler,
.pvReservedM12 = (void*) (0UL), /* Reserved */
.pvReservedM11 = (void*) (0UL), /* Reserved */
.pvReservedM10 = (void*) (0UL), /* Reserved */
.pvReservedM9 = (void*) (0UL), /* Reserved */
.pvReservedM8 = (void*) (0UL), /* Reserved */
.pvReservedM7 = (void*) (0UL), /* Reserved */
.pvReservedM6 = (void*) (0UL), /* Reserved */
.pfnSVCall_Handler = (void*) SVCall_Handler,
.pvReservedM4 = (void*) (0UL), /* Reserved */
.pvReservedM3 = (void*) (0UL), /* Reserved */
.pfnPendSV_Handler = (void*) PendSV_Handler,
.pfnSysTick_Handler = (void*) SysTick_Handler,
/* Configurable interrupts */
.pfnSYSTEM_Handler = (void*) SYSTEM_Handler, /* 0 Main Clock, 32k Oscillators Control, Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
.pfnWDT_Handler = (void*) WDT_Handler, /* 1 Watchdog Timer */
.pfnRTC_Handler = (void*) RTC_Handler, /* 2 Real-Time Counter */
.pfnEIC_Handler = (void*) EIC_Handler, /* 3 External Interrupt Controller */
.pfnFREQM_Handler = (void*) FREQM_Handler, /* 4 Frequency Meter */
#ifdef ID_USB
.pfnUSB_Handler = (void*) USB_Handler, /* 5 Universal Serial Bus */
#else
.pvReserved5 = (void*) (0UL), /* 5 Reserved */
#endif
.pfnNVMCTRL_Handler = (void*) NVMCTRL_Handler, /* 6 Non-Volatile Memory Controller */
.pfnDMAC_Handler = (void*) DMAC_Handler, /* 7 Direct Memory Access Controller */
.pfnEVSYS_Handler = (void*) EVSYS_Handler, /* 8 Event System Interface */
.pfnSERCOM0_Handler = (void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
.pfnSERCOM1_Handler = (void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
.pfnSERCOM2_Handler = (void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
#ifdef ID_SERCOM3
.pfnSERCOM3_Handler = (void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
#else
.pvReserved12 = (void*) (0UL), /* 12 Reserved */
#endif
#ifdef ID_SERCOM4
.pfnSERCOM4_Handler = (void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
#else
.pvReserved13 = (void*) (0UL), /* 13 Reserved */
#endif
#ifdef ID_SERCOM5
.pfnSERCOM5_Handler = (void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
#else
.pvReserved14 = (void*) (0UL), /* 14 Reserved */
#endif
.pfnTCC0_Handler = (void*) TCC0_Handler, /* 15 Timer Counter Control */
.pfnTC0_Handler = (void*) TC0_Handler, /* 16 Basic Timer Counter 0 */
.pfnTC1_Handler = (void*) TC1_Handler, /* 17 Basic Timer Counter 1 */
.pfnTC2_Handler = (void*) TC2_Handler, /* 18 Basic Timer Counter 2 */
.pfnTC3_Handler = (void*) TC3_Handler, /* 19 Basic Timer Counter 3 */
.pfnADC_Handler = (void*) ADC_Handler, /* 20 Analog Digital Converter */
.pfnAC_Handler = (void*) AC_Handler, /* 21 Analog Comparators */
#ifdef ID_PTC
.pfnPTC_Handler = (void*) PTC_Handler, /* 22 Peripheral Touch Controller */
#else
.pvReserved22 = (void*) (0UL), /* 22 Reserved */
#endif
.pfnSLCD_Handler = (void*) SLCD_Handler, /* 23 Segment Liquid Crystal Display Controller */
#ifdef ID_AES
.pfnAES_Handler = (void*) AES_Handler, /* 24 Advanced Encryption Standard */
#else
.pvReserved24 = (void*) (0UL), /* 24 Reserved */
#endif
#ifdef ID_TRNG
.pfnTRNG_Handler = (void*) TRNG_Handler /* 25 True Random Generator */
#else
.pvReserved25 = (void*) (0UL) /* 25 Reserved */
#endif
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

64
Smol Watch Project/My Project/Device_Startup/system_saml22.c
View file

@ -1,64 +0,0 @@
/**
* \file
*
* \brief Low-level initialization functions called upon chip startup.
*
* Copyright (c) 2018 Microchip Technology Inc.
*
* \asf_license_start
*
* \page License
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the "License"); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the Licence at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*
* \asf_license_stop
*
*/
#include "saml22.h"
/**
* Initial system clock frequency. The System RC Oscillator (RCSYS) provides
* the source for the main clock at chip startup.
*/
#define __SYSTEM_CLOCK (1000000)
uint32_t SystemCoreClock = __SYSTEM_CLOCK;/*!< System Clock Frequency (Core Clock)*/
/**
* Initialize the system
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
void SystemInit(void)
{
// Keep the default device state after reset
SystemCoreClock = __SYSTEM_CLOCK;
return;
}
/**
* Update SystemCoreClock variable
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
void SystemCoreClockUpdate(void)
{
// Not implemented
SystemCoreClock = __SYSTEM_CLOCK;
return;
}

169
Smol Watch Project/My Project/My Project.componentinfo.xml
View file

@ -1,169 +0,0 @@
<?xml version="1.0" encoding="utf-8"?>
<Store xmlns:i="http://www.w3.org/2001/XMLSchema-instance" xmlns="AtmelPackComponentManagement">
<ProjectComponents>
<ProjectComponent z:Id="i1" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/">
<CApiVersion></CApiVersion>
<CBundle></CBundle>
<CClass>CMSIS</CClass>
<CGroup>CORE</CGroup>
<CSub></CSub>
<CVariant></CVariant>
<CVendor>ARM</CVendor>
<CVersion>5.1.2</CVersion>
<DefaultRepoPath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs</DefaultRepoPath>
<DependentComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays" />
<Description></Description>
<Files xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
<d4p1:anyType i:type="FileInfo">
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Documentation\Core\html\index.html</AbsolutePath>
<Attribute></Attribute>
<Category>doc</Category>
<Condition></Condition>
<FileContentHash i:nil="true" />
<FileVersion></FileVersion>
<Name>CMSIS/Documentation/Core/html/index.html</Name>
<SelectString></SelectString>
<SourcePath></SourcePath>
</d4p1:anyType>
<d4p1:anyType i:type="FileInfo">
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\arm\CMSIS\5.4.0\CMSIS\Core\Include\</AbsolutePath>
<Attribute></Attribute>
<Category>include</Category>
<Condition></Condition>
<FileContentHash i:nil="true" />
<FileVersion></FileVersion>
<Name>CMSIS/Core/Include/</Name>
<SelectString></SelectString>
<SourcePath></SourcePath>
</d4p1:anyType>
</Files>
<PackName>CMSIS</PackName>
<PackPath>C:/Program Files (x86)/Atmel/Studio/7.0/Packs/arm/CMSIS/5.4.0/ARM.CMSIS.pdsc</PackPath>
<PackVersion>5.4.0</PackVersion>
<PresentInProject>true</PresentInProject>
<ReferenceConditionId>ARMv6_7_8-M Device</ReferenceConditionId>
<RteComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
<d4p1:string></d4p1:string>
</RteComponents>
<Status>Resolved</Status>
<VersionMode>Fixed</VersionMode>
<IsComponentInAtProject>true</IsComponentInAtProject>
</ProjectComponent>
<ProjectComponent z:Id="i2" xmlns:z="http://schemas.microsoft.com/2003/10/Serialization/">
<CApiVersion></CApiVersion>
<CBundle></CBundle>
<CClass>Device</CClass>
<CGroup>Startup</CGroup>
<CSub></CSub>
<CVariant></CVariant>
<CVendor>Atmel</CVendor>
<CVersion>1.2.0</CVersion>
<DefaultRepoPath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs</DefaultRepoPath>
<DependentComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
<d4p1:anyType z:Ref="i1" />
</DependentComponents>
<Description></Description>
<Files xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
<d4p1:anyType i:type="FileInfo">
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include</AbsolutePath>
<Attribute></Attribute>
<Category>include</Category>
<Condition>C</Condition>
<FileContentHash i:nil="true" />
<FileVersion></FileVersion>
<Name>include</Name>
<SelectString></SelectString>
<SourcePath></SourcePath>
</d4p1:anyType>
<d4p1:anyType i:type="FileInfo">
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\include\sam.h</AbsolutePath>
<Attribute></Attribute>
<Category>header</Category>
<Condition>C</Condition>
<FileContentHash>hIYDkoKMf0OfmYW7d/j2kw==</FileContentHash>
<FileVersion></FileVersion>
<Name>include/sam.h</Name>
<SelectString></SelectString>
<SourcePath></SourcePath>
</d4p1:anyType>
<d4p1:anyType i:type="FileInfo">
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\templates\main.c</AbsolutePath>
<Attribute>template</Attribute>
<Category>source</Category>
<Condition>C Exe</Condition>
<FileContentHash>D8GE7XTFu2b4QutVWp6lCg==</FileContentHash>
<FileVersion></FileVersion>
<Name>templates/main.c</Name>
<SelectString>Main file (.c)</SelectString>
<SourcePath></SourcePath>
</d4p1:anyType>
<d4p1:anyType i:type="FileInfo">
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\templates\main.cpp</AbsolutePath>
<Attribute>template</Attribute>
<Category>source</Category>
<Condition>C Exe</Condition>
<FileContentHash>nU+WlKcYaWh0AWBBS+WVpA==</FileContentHash>
<FileVersion></FileVersion>
<Name>templates/main.cpp</Name>
<SelectString>Main file (.cpp)</SelectString>
<SourcePath></SourcePath>
</d4p1:anyType>
<d4p1:anyType i:type="FileInfo">
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\gcc\system_saml22.c</AbsolutePath>
<Attribute>config</Attribute>
<Category>source</Category>
<Condition>GCC Exe</Condition>
<FileContentHash>PrvYHyBfxNZHSGYPLxcSug==</FileContentHash>
<FileVersion></FileVersion>
<Name>gcc/system_saml22.c</Name>
<SelectString></SelectString>
<SourcePath></SourcePath>
</d4p1:anyType>
<d4p1:anyType i:type="FileInfo">
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\gcc\gcc\startup_saml22.c</AbsolutePath>
<Attribute>config</Attribute>
<Category>source</Category>
<Condition>GCC Exe</Condition>
<FileContentHash>BLzyJq7J25P7XTztxvVwNw==</FileContentHash>
<FileVersion></FileVersion>
<Name>gcc/gcc/startup_saml22.c</Name>
<SelectString></SelectString>
<SourcePath></SourcePath>
</d4p1:anyType>
<d4p1:anyType i:type="FileInfo">
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\gcc\gcc\saml22j18a_flash.ld</AbsolutePath>
<Attribute>config</Attribute>
<Category>linkerScript</Category>
<Condition>GCC Exe</Condition>
<FileContentHash>Ys4aTlim2ZJU0Qo003K8VQ==</FileContentHash>
<FileVersion></FileVersion>
<Name>gcc/gcc/saml22j18a_flash.ld</Name>
<SelectString></SelectString>
<SourcePath></SourcePath>
</d4p1:anyType>
<d4p1:anyType i:type="FileInfo">
<AbsolutePath>C:/Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\SAML22_DFP\1.2.77\gcc\gcc\saml22j18a_sram.ld</AbsolutePath>
<Attribute>config</Attribute>
<Category>other</Category>
<Condition>GCC Exe</Condition>
<FileContentHash>hDqTHEM9gCdn4WKPS2tHzg==</FileContentHash>
<FileVersion></FileVersion>
<Name>gcc/gcc/saml22j18a_sram.ld</Name>
<SelectString></SelectString>
<SourcePath></SourcePath>
</d4p1:anyType>
</Files>
<PackName>SAML22_DFP</PackName>
<PackPath>C:/Program Files (x86)/Atmel/Studio/7.0/Packs/atmel/SAML22_DFP/1.2.77/Atmel.SAML22_DFP.pdsc</PackPath>
<PackVersion>1.2.77</PackVersion>
<PresentInProject>true</PresentInProject>
<ReferenceConditionId>ATSAML22J18A</ReferenceConditionId>
<RteComponents xmlns:d4p1="http://schemas.microsoft.com/2003/10/Serialization/Arrays">
<d4p1:string></d4p1:string>
</RteComponents>
<Status>Resolved</Status>
<VersionMode>Fixed</VersionMode>
<IsComponentInAtProject>true</IsComponentInAtProject>
</ProjectComponent>
</ProjectComponents>
</Store>

1040
Smol Watch Project/My Project/My Project.cproj
View file

File diff suppressed because it is too large Load diff

9
Smol Watch Project/My Project/atmel_start.c
View file

@ -1,9 +0,0 @@
#include <atmel_start.h>
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void)
{
system_init();
}

18
Smol Watch Project/My Project/atmel_start.h
View file

@ -1,18 +0,0 @@
#ifndef ATMEL_START_H_INCLUDED
#define ATMEL_START_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include "driver_init.h"
/**
* Initializes MCU, drivers and middleware in the project
**/
void atmel_start_init(void);
#ifdef __cplusplus
}
#endif
#endif

67
Smol Watch Project/My Project/atmel_start_pins.h
View file

@ -1,67 +0,0 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef ATMEL_START_PINS_H_INCLUDED
#define ATMEL_START_PINS_H_INCLUDED
#include <hal_gpio.h>
// SAML22 has 9 pin functions
#define GPIO_PIN_FUNCTION_A 0
#define GPIO_PIN_FUNCTION_B 1
#define GPIO_PIN_FUNCTION_C 2
#define GPIO_PIN_FUNCTION_D 3
#define GPIO_PIN_FUNCTION_E 4
#define GPIO_PIN_FUNCTION_F 5
#define GPIO_PIN_FUNCTION_G 6
#define GPIO_PIN_FUNCTION_H 7
#define GPIO_PIN_FUNCTION_I 8
#define VBUS_DET GPIO(GPIO_PORTA, 2)
#define SEG1 GPIO(GPIO_PORTA, 4)
#define SEG2 GPIO(GPIO_PORTA, 5)
#define SEG3 GPIO(GPIO_PORTA, 6)
#define SEG4 GPIO(GPIO_PORTA, 7)
#define SEG5 GPIO(GPIO_PORTA, 8)
#define SEG6 GPIO(GPIO_PORTA, 9)
#define SEG7 GPIO(GPIO_PORTA, 10)
#define SEG8 GPIO(GPIO_PORTA, 11)
#define SEG14 GPIO(GPIO_PORTA, 12)
#define SEG15 GPIO(GPIO_PORTA, 13)
#define SEG16 GPIO(GPIO_PORTA, 14)
#define SEG17 GPIO(GPIO_PORTA, 15)
#define SEG18 GPIO(GPIO_PORTA, 16)
#define SEG19 GPIO(GPIO_PORTA, 17)
#define SEG20 GPIO(GPIO_PORTA, 18)
#define SEG21 GPIO(GPIO_PORTA, 19)
#define RED GPIO(GPIO_PORTA, 20)
#define GREEN GPIO(GPIO_PORTA, 21)
#define BTN_LIGHT GPIO(GPIO_PORTA, 22)
#define BTN_MODE GPIO(GPIO_PORTA, 23)
#define BUZZER GPIO(GPIO_PORTA, 27)
#define D1 GPIO(GPIO_PORTB, 0)
#define A1 GPIO(GPIO_PORTB, 1)
#define A2 GPIO(GPIO_PORTB, 2)
#define D0 GPIO(GPIO_PORTB, 3)
#define A0 GPIO(GPIO_PORTB, 4)
#define BTN_ALARM GPIO(GPIO_PORTB, 5)
#define COM0 GPIO(GPIO_PORTB, 6)
#define COM1 GPIO(GPIO_PORTB, 7)
#define COM2 GPIO(GPIO_PORTB, 8)
#define SEG0 GPIO(GPIO_PORTB, 9)
#define SEG9 GPIO(GPIO_PORTB, 11)
#define SEG10 GPIO(GPIO_PORTB, 12)
#define SEG11 GPIO(GPIO_PORTB, 13)
#define SEG12 GPIO(GPIO_PORTB, 14)
#define SEG13 GPIO(GPIO_PORTB, 15)
#define SEG22 GPIO(GPIO_PORTB, 16)
#define SEG23 GPIO(GPIO_PORTB, 17)
#define SDA GPIO(GPIO_PORTB, 30)
#define SCL GPIO(GPIO_PORTB, 31)
#endif // ATMEL_START_PINS_H_INCLUDED

328
Smol Watch Project/My Project/driver_init.c
View file

@ -1,328 +0,0 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_init.h"
#include <peripheral_clk_config.h>
#include <utils.h>
#include <hal_init.h>
#include <hpl_adc_base.h>
struct slcd_sync_descriptor SEGMENT_LCD_0;
struct adc_sync_descriptor ADC_0;
struct calendar_descriptor CALENDAR_0;
struct i2c_m_sync_desc I2C_0;
struct pwm_descriptor PWM_1;
void ADC_0_PORT_init(void)
{
// Disable digital pin circuitry
gpio_set_pin_direction(A1, GPIO_DIRECTION_OFF);
gpio_set_pin_function(A1, PINMUX_PB01B_ADC_AIN9);
// Disable digital pin circuitry
gpio_set_pin_direction(A2, GPIO_DIRECTION_OFF);
gpio_set_pin_function(A2, PINMUX_PB02B_ADC_AIN10);
// Disable digital pin circuitry
gpio_set_pin_direction(A0, GPIO_DIRECTION_OFF);
gpio_set_pin_function(A0, PINMUX_PB04B_ADC_AIN12);
}
void ADC_0_CLOCK_init(void)
{
hri_mclk_set_APBCMASK_ADC_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, ADC_GCLK_ID, CONF_GCLK_ADC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}
void ADC_0_init(void)
{
ADC_0_CLOCK_init();
ADC_0_PORT_init();
adc_sync_init(&ADC_0, ADC, (void *)NULL);
}
void EXTERNAL_IRQ_0_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, EIC_GCLK_ID, CONF_GCLK_EIC_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBAMASK_EIC_bit(MCLK);
// Set pin direction to input
gpio_set_pin_direction(BTN_ALARM, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(BTN_ALARM,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_DOWN);
gpio_set_pin_function(BTN_ALARM, PINMUX_PB05A_EIC_EXTINT5);
// Set pin direction to input
gpio_set_pin_direction(BTN_LIGHT, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(BTN_LIGHT,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_DOWN);
gpio_set_pin_function(BTN_LIGHT, PINMUX_PA22A_EIC_EXTINT6);
// Set pin direction to input
gpio_set_pin_direction(BTN_MODE, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(BTN_MODE,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_DOWN);
gpio_set_pin_function(BTN_MODE, PINMUX_PA23A_EIC_EXTINT7);
ext_irq_init();
}
void CALENDAR_0_CLOCK_init(void)
{
hri_mclk_set_APBAMASK_RTC_bit(MCLK);
}
void CALENDAR_0_init(void)
{
CALENDAR_0_CLOCK_init();
calendar_init(&CALENDAR_0, RTC);
}
void I2C_0_PORT_init(void)
{
gpio_set_pin_pull_mode(SDA,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(SDA, PINMUX_PB30C_SERCOM1_PAD0);
gpio_set_pin_pull_mode(SCL,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_OFF);
gpio_set_pin_function(SCL, PINMUX_PB31C_SERCOM1_PAD1);
}
void I2C_0_CLOCK_init(void)
{
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_CORE, CONF_GCLK_SERCOM1_CORE_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_gclk_write_PCHCTRL_reg(GCLK, SERCOM1_GCLK_ID_SLOW, CONF_GCLK_SERCOM1_SLOW_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
hri_mclk_set_APBCMASK_SERCOM1_bit(MCLK);
}
void I2C_0_init(void)
{
I2C_0_CLOCK_init();
i2c_m_sync_init(&I2C_0, SERCOM1);
I2C_0_PORT_init();
}
void delay_driver_init(void)
{
delay_init(SysTick);
}
void PWM_0_PORT_init(void)
{
gpio_set_pin_function(RED, PINMUX_PA20E_TC3_WO0);
gpio_set_pin_function(GREEN, PINMUX_PA21E_TC3_WO1);
}
void PWM_0_CLOCK_init(void)
{
hri_mclk_set_APBCMASK_TC3_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, TC3_GCLK_ID, CONF_GCLK_TC3_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}
void PWM_1_PORT_init(void)
{
gpio_set_pin_function(BUZZER, PINMUX_PA27F_TCC0_WO5);
}
void PWM_1_CLOCK_init(void)
{
hri_mclk_set_APBCMASK_TCC0_bit(MCLK);
hri_gclk_write_PCHCTRL_reg(GCLK, TCC0_GCLK_ID, CONF_GCLK_TCC0_SRC | (1 << GCLK_PCHCTRL_CHEN_Pos));
}
void PWM_1_init(void)
{
PWM_1_CLOCK_init();
PWM_1_PORT_init();
pwm_init(&PWM_1, TCC0, _tcc_get_pwm());
}
void SEGMENT_LCD_0_PORT_init(void)
{
gpio_set_pin_function(COM0, PINMUX_PB06B_SLCD_LP0);
gpio_set_pin_function(COM1, PINMUX_PB07B_SLCD_LP1);
gpio_set_pin_function(COM2, PINMUX_PB08B_SLCD_LP2);
gpio_set_pin_function(SEG0, PINMUX_PB09B_SLCD_LP3);
gpio_set_pin_function(SEG1, PINMUX_PA04B_SLCD_LP4);
gpio_set_pin_function(SEG2, PINMUX_PA05B_SLCD_LP5);
gpio_set_pin_function(SEG3, PINMUX_PA06B_SLCD_LP6);
gpio_set_pin_function(SEG4, PINMUX_PA07B_SLCD_LP7);
gpio_set_pin_function(SEG5, PINMUX_PA08B_SLCD_LP11);
gpio_set_pin_function(SEG6, PINMUX_PA09B_SLCD_LP12);
gpio_set_pin_function(SEG7, PINMUX_PA10B_SLCD_LP13);
gpio_set_pin_function(SEG8, PINMUX_PA11B_SLCD_LP14);
gpio_set_pin_function(SEG9, PINMUX_PB11B_SLCD_LP21);
gpio_set_pin_function(SEG10, PINMUX_PB12B_SLCD_LP22);
gpio_set_pin_function(SEG11, PINMUX_PB13B_SLCD_LP23);
gpio_set_pin_function(SEG12, PINMUX_PB14B_SLCD_LP24);
gpio_set_pin_function(SEG13, PINMUX_PB15B_SLCD_LP25);
gpio_set_pin_function(SEG14, PINMUX_PA12B_SLCD_LP28);
gpio_set_pin_function(SEG15, PINMUX_PA13B_SLCD_LP29);
gpio_set_pin_function(SEG16, PINMUX_PA14B_SLCD_LP30);
gpio_set_pin_function(SEG17, PINMUX_PA15B_SLCD_LP31);
gpio_set_pin_function(SEG18, PINMUX_PA16B_SLCD_LP32);
gpio_set_pin_function(SEG19, PINMUX_PA17B_SLCD_LP33);
gpio_set_pin_function(SEG20, PINMUX_PA18B_SLCD_LP34);
gpio_set_pin_function(SEG21, PINMUX_PA19B_SLCD_LP35);
gpio_set_pin_function(SEG22, PINMUX_PB16B_SLCD_LP42);
gpio_set_pin_function(SEG23, PINMUX_PB17B_SLCD_LP43);
}
/**
* \brief SLCD initialization function
*
* Enables SLCD peripheral, clocks and initializes SLCD driver
*/
void SEGMENT_LCD_0_init(void)
{
hri_mclk_set_APBCMASK_SLCD_bit(SLCD);
slcd_sync_init(&SEGMENT_LCD_0, SLCD);
SEGMENT_LCD_0_PORT_init();
}
void system_init(void)
{
init_mcu();
/*
// GPIO on PA02
// Set pin direction to input
gpio_set_pin_direction(VBUS_DET, GPIO_DIRECTION_IN);
gpio_set_pin_pull_mode(VBUS_DET,
// <y> Pull configuration
// <id> pad_pull_config
// <GPIO_PULL_OFF"> Off
// <GPIO_PULL_UP"> Pull-up
// <GPIO_PULL_DOWN"> Pull-down
GPIO_PULL_DOWN);
gpio_set_pin_function(VBUS_DET, GPIO_PIN_FUNCTION_OFF);
// GPIO on PB00
gpio_set_pin_level(D1,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(D1, GPIO_DIRECTION_OUT);
gpio_set_pin_function(D1, GPIO_PIN_FUNCTION_OFF);
// GPIO on PB03
gpio_set_pin_level(D0,
// <y> Initial level
// <id> pad_initial_level
// <false"> Low
// <true"> High
false);
// Set pin direction to output
gpio_set_pin_direction(D0, GPIO_DIRECTION_OUT);
gpio_set_pin_function(D0, GPIO_PIN_FUNCTION_OFF);
ADC_0_init();
EXTERNAL_IRQ_0_init();
CALENDAR_0_init();
I2C_0_init();
delay_driver_init();
PWM_0_CLOCK_init();
PWM_0_PORT_init();
PWM_0_init();
PWM_1_init();
SEGMENT_LCD_0_init();
*/
}

84
Smol Watch Project/My Project/driver_init.h
View file

@ -1,84 +0,0 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_INIT_INCLUDED
#define DRIVER_INIT_INCLUDED
#include "atmel_start_pins.h"
#ifdef __cplusplus
extern "C" {
#endif
#include <hal_atomic.h>
#include <hal_delay.h>
#include <hal_gpio.h>
#include <hal_init.h>
#include <hal_io.h>
#include <hal_sleep.h>
#include <hal_adc_sync.h>
#include <hal_ext_irq.h>
#include <hal_calendar.h>
#include <hal_i2c_m_sync.h>
#include <hal_delay.h>
#include <tc_lite.h>
#include <hal_pwm.h>
#include <hpl_tcc.h>
#include <hal_slcd_sync.h>
extern struct adc_sync_descriptor ADC_0;
extern struct calendar_descriptor CALENDAR_0;
extern struct i2c_m_sync_desc I2C_0;
extern struct pwm_descriptor PWM_1;
extern struct slcd_sync_descriptor SEGMENT_LCD_0;
void ADC_0_PORT_init(void);
void ADC_0_CLOCK_init(void);
void ADC_0_init(void);
void CALENDAR_0_CLOCK_init(void);
void CALENDAR_0_init(void);
void I2C_0_CLOCK_init(void);
void I2C_0_init(void);
void I2C_0_PORT_init(void);
void delay_driver_init(void);
void PWM_0_CLOCK_init(void);
void PWM_0_PORT_init(void);
int8_t PWM_0_init(void);
void PWM_1_PORT_init(void);
void PWM_1_CLOCK_init(void);
void PWM_1_init(void);
void EXTERNAL_IRQ_0_init(void);
void SEGMENT_LCD_0_init(void);
/**
* \brief Perform system initialization, initialize pins and clocks for
* peripherals
*/
void system_init(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_INIT_INCLUDED

117
Smol Watch Project/My Project/examples/driver_examples.c
View file

@ -1,117 +0,0 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#include "driver_examples.h"
#include "driver_init.h"
#include "utils.h"
/**
* Example of using ADC_0 to generate waveform.
*/
void ADC_0_example(void)
{
uint8_t buffer[2];
adc_sync_enable_channel(&ADC_0, 0);
while (1) {
adc_sync_read_channel(&ADC_0, 0, buffer, 2);
}
}
static void button_on_PB05_pressed(void)
{
}
static void button_on_PA22_pressed(void)
{
}
static void button_on_PA23_pressed(void)
{
}
/**
* Example of using EXTERNAL_IRQ_0
*/
void EXTERNAL_IRQ_0_example(void)
{
ext_irq_register(PIN_PB05, button_on_PB05_pressed);
ext_irq_register(PIN_PA22, button_on_PA22_pressed);
ext_irq_register(PIN_PA23, button_on_PA23_pressed);
}
/**
* Example of using CALENDAR_0.
*/
static struct calendar_alarm alarm;
static void alarm_cb(struct calendar_descriptor *const descr)
{
/* alarm expired */
}
void CALENDAR_0_example(void)
{
struct calendar_date date;
struct calendar_time time;
calendar_enable(&CALENDAR_0);
date.year = 2000;
date.month = 12;
date.day = 31;
time.hour = 12;
time.min = 59;
time.sec = 59;
calendar_set_date(&CALENDAR_0, &date);
calendar_set_time(&CALENDAR_0, &time);
alarm.cal_alarm.datetime.time.sec = 4;
alarm.cal_alarm.option = CALENDAR_ALARM_MATCH_SEC;
alarm.cal_alarm.mode = REPEAT;
calendar_set_alarm(&CALENDAR_0, &alarm, alarm_cb);
}
void I2C_0_example(void)
{
struct io_descriptor *I2C_0_io;
i2c_m_sync_get_io_descriptor(&I2C_0, &I2C_0_io);
i2c_m_sync_enable(&I2C_0);
i2c_m_sync_set_slaveaddr(&I2C_0, 0x12, I2C_M_SEVEN);
io_write(I2C_0_io, (uint8_t *)"Hello World!", 12);
}
void delay_example(void)
{
delay_ms(5000);
}
/**
* Example of using PWM_1.
*/
void PWM_1_example(void)
{
pwm_set_parameters(&PWM_1, 10000, 5000);
pwm_enable(&PWM_1);
}
#define SLCD_EXAMPLE_SEGID SLCD_SEGID(1, 0)
/**
* Example of using SEGMENT_LCD_0
*/
void SEGMENT_LCD_0_example(void)
{
slcd_sync_enable(&SEGMENT_LCD_0);
slcd_sync_seg_on(&SEGMENT_LCD_0, SLCD_EXAMPLE_SEGID);
}

32
Smol Watch Project/My Project/examples/driver_examples.h
View file

@ -1,32 +0,0 @@
/*
* Code generated from Atmel Start.
*
* This file will be overwritten when reconfiguring your Atmel Start project.
* Please copy examples or other code you want to keep to a separate file
* to avoid losing it when reconfiguring.
*/
#ifndef DRIVER_EXAMPLES_H_INCLUDED
#define DRIVER_EXAMPLES_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
void ADC_0_example(void);
void EXTERNAL_IRQ_0_example(void);
void CALENDAR_0_example(void);
void I2C_0_example(void);
void delay_example(void);
void PWM_1_example(void);
void SEGMENT_LCD_0_example(void);
#ifdef __cplusplus
}
#endif
#endif // DRIVER_EXAMPLES_H_INCLUDED

74
Smol Watch Project/My Project/hal/documentation/adc_sync.rst
View file

@ -1,74 +0,0 @@
======================
ADC Synchronous driver
======================
An ADC (Analog-to-Digital Converter) converts analog signals to digital values.
A reference signal with a known voltage level is quantified into equally
sized chunks, each representing a digital value from 0 to the highest number
possible with the bit resolution supported by the ADC. The input voltage
measured by the ADC is compared against these chunks and the chunk with the
closest voltage level defines the digital value that can be used to represent
the analog input voltage level.
Usually an ADC can operate in either differential or single-ended mode.
In differential mode two signals (V+ and V-) are compared against each other
and the resulting digital value represents the relative voltage level between
V+ and V-. This means that if the input voltage level on V+ is lower than on
V- the digital value is negative, which also means that in differential
mode one bit is lost to the sign. In single-ended mode only V+ is compared
against the reference voltage, and the resulting digital value can only be
positive, but the full bit-range of the ADC can be used.
Usually multiple resolutions are supported by the ADC, lower resolution can
reduce the conversion time, but lose accuracy.
Some ADCs has a gain stage on the input lines which can be used to increase the
dynamic range. The default gain value is usually x1, which means that the
conversion range is from 0V to the reference voltage.
Applications can change the gain stage, to increase or reduce the conversion
range.
The window mode allows the conversion result to be compared to a set of
predefined threshold values. Applications can use callback function to monitor
if the conversion result exceeds predefined threshold value.
Usually multiple reference voltages are supported by the ADC, both internal and
external with difference voltage levels. The reference voltage have an impact
on the accuracy, and should be selected to cover the full range of the analog
input signal and never less than the expected maximum input voltage.
There are two conversion modes supported by ADC, single shot and free running.
In single shot mode the ADC only make one conversion when triggered by the
application, in free running mode it continues to make conversion from it
is triggered until it is stopped by the application. When window monitoring,
the ADC should be set to free running mode.
Features
--------
* Initialization and de-initialization
* Support multiple Conversion Mode, Single or Free run
* Start ADC Conversion
* Read Conversion Result
Applications
------------
* Measurement of internal sensor. E.g., MCU internal temperature sensor value.
* Measurement of external sensor. E.g., Temperature, humidity sensor value.
* Sampling and measurement of a signal. E.g., sinusoidal wave, square wave.
Dependencies
------------
* ADC hardware
Concurrency
-----------
N/A
Limitations
-----------
N/A
Knows issues and workarounds
----------------------------
N/A

72
Smol Watch Project/My Project/hal/documentation/calendar.rst
View file

@ -1,72 +0,0 @@
===============================
The Calendar driver (bare-bone)
===============================
The Calendar driver provides means to set and get current date and time.
After enabling, an instance of the driver starts counting time from the base date with
the resolution of one second. The default base date is 00:00:00 1st of January 1970.
Only the base year of the base date can be changed via the driver API.
The current date and time is kept internally in a relative form as the difference between
current date and time and the base date and time. This means that changing the base year changes
current date.
The base date and time defines time "zero" or the earliest possible point in time that the calender driver can describe,
this means that current time and alarms can not be set to anything earlier than this time.
The Calendar driver provides alarm functionality.
An alarm is a software trigger which fires on particular date and time with particular periodicity.
Upon firing the given callback function is called.
An alarm can be in single-shot mode, firing only once at matching time; or in repeating mode, meaning that it will
reschedule a new alarm automatically based on repeating mode configuration.
In single-shot mode an alarm is removed from the alarm queue before its callback is called. It allows an application to
reuse the memory of expired alarm in the callback.
An alarm can be triggered on the following events: match on second, minute, hour, day, month or year.
Matching on second means that the alarm is triggered when the value of seconds of the current time is equal to
the alarm's value of seconds. This means repeating alarm with match on seconds is triggered with the period of a minute.
Matching on minute means that the calendars minute and seconds values has to match the alarms, the rest of the date-time
value is ignored. In repeating mode this means a new alarm every hour.
The same logic is applied to match on hour, day, month and year.
Each instance of the Calendar driver supports infinite amount of software alarms, only limited by the amount of RAM available.
Features
--------
* Initialization and de-initialization
* Enabling and disabling
* Date and time operations
* Software alarms
Applications
------------
* A source of current date and time for an embedded system.
* Periodical functionality in low-power applications since the driver is designed to use 1Hz clock.
* Periodical function calls in case if it is more convenient to operate with absolute time.
Dependencies
------------
* This driver expects a counter to be increased by one every second to count date and time correctly.
* Each instance of the driver requires separate hardware timer.
Concurrency
-----------
The Calendar driver is an interrupt driven driver.This means that the interrupt that triggers an alarm may occur during
the process of adding or removing an alarm via the driver's API. In such case the interrupt processing is postponed
until the alarm adding or removing is complete.
The alarm queue is not protected from the access by interrupts not used by the driver. Due to this
it is not recommended to add or remove an alarm from such interrupts: in case if a higher priority interrupt supersedes
the driver's interrupt, adding or removing an alarm may cause unpredictable behavior of the driver.
Limitations
-----------
* Only years divisible by 4 are deemed a leap year, this gives a correct result between the years 1901 to 2099.
* The driver is designed to work outside of an operating system environment, the software alarm queue is therefore processed in interrupt context which may delay execution of other interrupts.
* If there are a lot of frequently called interrupts with the priority higher than the driver's one, it may cause delay in alarm's triggering.
* Changing the base year or setting current date or time does not shift alarms' date and time accordingly or expires alarms.
Knows issues and workarounds
----------------------------
Not applicable

39
Smol Watch Project/My Project/hal/documentation/ext_irq.rst
View file

@ -1,39 +0,0 @@
==============
EXT IRQ driver
==============
The External Interrupt driver allows external pins to be
configured as interrupt lines. Each interrupt line can be
individually masked and can generate an interrupt on rising,
falling or both edges, or on high or low levels. Some of
external pin can also be configured to wake up the device
from sleep modes where all clocks have been disabled.
External pins can also generate an event.
Features
--------
* Initialization and de-initialization
* Enabling and disabling
* Detect external pins interrupt
Applications
------------
* Generate an interrupt on rising, falling or both edges,
or on high or low levels.
Dependencies
------------
* GPIO hardware
Concurrency
-----------
N/A
Limitations
-----------
N/A
Knows issues and workarounds
----------------------------
N/A

87
Smol Watch Project/My Project/hal/documentation/i2c_master_sync.rst
View file

@ -1,87 +0,0 @@
=============================
I2C Master synchronous driver
=============================
I2C (Inter-Integrated Circuit) is a two wire serial interface usually used
for on-board low-speed bi-directional communication between controllers and
peripherals. The master device is responsible for initiating and controlling
all transfers on the I2C bus. Only one master device can be active on the I2C
bus at the time, but the master role can be transferred between devices on the
same I2C bus. I2C uses only two bidirectional open-drain lines, usually
designated SDA (Serial Data Line) and SCL (Serial Clock Line), with pull up
resistors.
The stop condition is automatically controlled by the driver if the I/O write and
read functions are used, but can be manually controlled by using the
i2c_m_sync_transfer function.
Often a master accesses different information in the slave by accessing
different registers in the slave. This is done by first sending a message to
the target slave containing the register address, followed by a repeated start
condition (no stop condition between) ending with transferring register data.
This scheme is supported by the i2c_m_sync_cmd_write and i2c_m_sync_cmd_read
function, but limited to 8-bit register addresses.
I2C Modes (standard mode/fastmode+/highspeed mode) can only be selected in
Atmel Start. If the SCL frequency (baudrate) has changed run-time, make sure to
stick within the SCL clock frequency range supported by the selected mode.
The requested SCL clock frequency is not validated by the
i2c_m_sync_set_baudrate function against the selected I2C mode.
Features
--------
* I2C Master support
* Initialization and de-initialization
* Enabling and disabling
* Run-time bus speed configuration
* Write and read I2C messages
* Slave register access functions (limited to 8-bit address)
* Manual or automatic stop condition generation
* 10- and 7- bit addressing
* I2C Modes supported
+----------------------+-------------------+
|* Standard/Fast mode | (SCL: 1 - 400kHz) |
+----------------------+-------------------+
|* Fastmode+ | (SCL: 1 - 1000kHz)|
+----------------------+-------------------+
|* Highspeed mode | (SCL: 1 - 3400kHz)|
+----------------------+-------------------+
Applications
------------
* Transfer data to and from one or multiple I2C slaves like I2C connected sensors, data storage or other I2C capable peripherals
* Data communication between micro controllers
* Controlling displays
Dependencies
------------
* I2C Master capable hardware
Concurrency
-----------
N/A
Limitations
-----------
General
^^^^^^^
* System Managmenet Bus (SMBus) not supported.
* Power Management Bus (PMBus) not supported.
Clock considerations
^^^^^^^^^^^^^^^^^^^^
The register value for the requested I2C speed is calculated and placed in the correct register, but not validated if it works correctly with the clock/prescaler settings used for the module. To validate the I2C speed setting use the formula found in the configuration file for the module. Selectable speed is automatically limited within the speed range defined by the I2C mode selected.
Known issues and workarounds
----------------------------
N/A

53
Smol Watch Project/My Project/hal/documentation/pwm.rst
View file

@ -1,53 +0,0 @@
The PWM Driver(bare-bone)
=========================
Pulse-width modulation (PWM) is used to create an analog behavior
digitally by controlling the amount of power transferred to the
connected peripheral. This is achieved by controlling the high period
(duty-cycle) of a periodic signal.
User can change the period or duty cycle whenever PWM is running. The
function pwm_set_parameters is used to configure these two parameters.
Note these are raw register values and the parameter duty_cycle means
the period of first half during one cycle, which should be not beyond
total period value.
In addition, user can also get multi PWM channels output from different
peripherals at the same time, which is implemented more flexible by the
function pointers.
Features
--------
* Initialization/de-initialization
* Enabling/disabling
* Run-time control of PWM duty-cycle and period
* Notifications about errors and one PWM cycle is done
Applications
------------
Motor control, ballast, LED, H-bridge, power converters, and
other types of power control applications.
Dependencies
------------
The peripheral which can perform waveform generation like frequency
generation and pulse-width modulation, such as Timer/Counter.
Concurrency
-----------
N/A
Limitations
-----------
The current driver doesn't support the features like recoverable,
non-recoverable faults, dithering, dead-time insertion.
Known issues and workarounds
----------------------------
N/A

82
Smol Watch Project/My Project/hal/documentation/slcd_sync.rst
View file

@ -1,82 +0,0 @@
SLCD Synchronous driver
=======================
An LCD display is made of several segments (pixels or complete symbols) which
can be block light or let light through. In each segment is one electrode
connected to the common terminal (COM pin) and one is connected to the segment
terminal (SEG pin). When a voltage above a certain threshold level is applied
across the liquid crystal, it will change orientation and either let light
through or block it.
The driver supports segment on/off/blink, animation and character display.
Each segment has a unique int32 segment id which is used by the driver. The id is
combined by common number(COM) and segment number(SEG), the COM and SEG start from 0.
The unique segment id is calculated by this formula: (COM << 16) | SEG
For example a 8(coms)*8(segments)SLCD, the unique segment id for segment should be
+-----+-----+---------+
| COM | SEG | ID |
+-----+-----+---------+
| 0 | 0 | 0x00000 |
+-----+-----+---------+
| 1 | 0 | 0x10000 |
+-----+-----+---------+
| 7 | 7 | 0x70007 |
+-----+-----+---------+
Segment ID can be calculated using the pre-defined macro SLCD_SEGID(com, seg).
For character display, the "segment character mapping table" and "character mapping table"
should be setup in configuration. The driver have no API to setup/change those
mapping setting.
There are two pre-defined "segment character mapping table" in this driver, 7 segments
and 14 segments. The 7 segment character mapping can display 0-9 and a-f, the 14
segments character mapping can display 0-9, A-Z and some special ASCII, for more
details please refer to hpl_slcd_cm_7_seg_mapping.h and hpl_slcd_cm_14_seg_mapping.h.
Application can also adjust this mapping table in the configuration header file,
to add more character mapping or remove some unused character.
The "character mapping" is used to setup each character in SLCD display screen.
The driver supports multiple character mapping, the max number varies on different
MCU/MPU. For example if an LCD display screen has five "7-segments character" and
eight "14-segments character", and the MCU support max 44 characters setting, then
the 13 character should be setup in configuration. Application can select any
position from those 44 characters setting to save those 13 character.
The index of character setting will be used in the driver API. For example:
five "7-segments character" setting to 0 to 4 and eight "14-segments character" setting
to 10 to 17. Then the application can use index from 0 to 4 to display the
"7-segments character" and use index from 10 to 14 to display "14-segments character".
Features
--------
* Initialization and de-initialization
* Enabling and Disabling
* Switching segment on/off
* Set segment blink
* Autonomous animation
* Character display
Applications
------------
* SLCD display control, segment on/off/blink
* Play battery animation, running wheel, wifi signal, etc.
* Display Time Clock by 7 segments character mapping
* Display ASCII character by 14 segments character mapping
Dependencies
------------
* SLCD capable hardware
Concurrency
-----------
N/A
Limitations
-----------
Known issues and workarounds
----------------------------
N/A

277
Smol Watch Project/My Project/hal/include/hal_adc_sync.h
View file

@ -1,277 +0,0 @@
/**
* \file
*
* \brief ADC functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_ADC_SYNC_H_INCLUDED
#define _HAL_ADC_SYNC_H_INCLUDED
#include <hpl_adc_sync.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_adc_sync
*
* @{
*/
/**
* \brief ADC descriptor
*
* The ADC descriptor forward declaration.
*/
struct adc_sync_descriptor;
/**
* \brief ADC descriptor
*/
struct adc_sync_descriptor {
/** ADC device */
struct _adc_sync_device device;
};
/**
* \brief Initialize ADC
*
* This function initializes the given ADC descriptor.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[out] descr An ADC descriptor to initialize
* \param[in] hw The pointer to hardware instance
* \param[in] func The pointer to a set of functions pointers
*
* \return Initialization status.
*/
int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func);
/**
* \brief Deinitialize ADC
*
* This function deinitializes the given ADC descriptor.
* It checks if the given hardware is initialized and if the given hardware is
* permitted to be deinitialized.
*
* \param[in] descr An ADC descriptor to deinitialize
*
* \return De-initialization status.
*/
int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr);
/**
* \brief Enable ADC
*
* Use this function to set the ADC peripheral to enabled state.
*
* \param[in] descr Pointer to the ADC descriptor
* \param[in] channel Channel number
*
* \return Operation status
*
*/
int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
/**
* \brief Disable ADC
*
* Use this function to set the ADC peripheral to disabled state.
*
* \param[in] descr Pointer to the ADC descriptor
* \param[in] channel Channel number
*
* \return Operation status
*
*/
int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel);
/**
* \brief Read data from ADC
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
* \param[in] buf A buffer to read data to
* \param[in] length The size of a buffer
*
* \return The number of bytes read.
*/
int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
const uint16_t length);
/**
* \brief Set ADC reference source
*
* This function sets ADC reference source.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] reference A reference source to set
*
* \return Status of the ADC reference source setting.
*/
int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference);
/**
* \brief Set ADC resolution
*
* This function sets ADC resolution.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] resolution A resolution to set
*
* \return Status of the ADC resolution setting.
*/
int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* This function sets ADC positive and negative input sources.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*
* \return Status of the ADC channels setting.
*/
int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set ADC conversion mode
*
* This function sets ADC conversion mode.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] mode A conversion mode to set
*
* \return Status of the ADC conversion mode setting.
*/
int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode);
/**
* \brief Set ADC differential mode
*
* This function sets ADC differential mode.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*
* \return Status of the ADC differential mode setting.
*/
int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set ADC channel gain
*
* This function sets ADC channel gain.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
* \param[in] gain A gain to set
*
* \return Status of the ADC gain setting.
*/
int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel,
const adc_gain_t gain);
/**
* \brief Set ADC window mode
*
* This function sets ADC window mode.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] mode A window mode to set
*
* \return Status of the ADC window mode setting.
*/
int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode);
/**
* \brief Set ADC thresholds
*
* This function sets ADC positive and negative thresholds.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] low_threshold A lower thresholds to set
* \param[in] up_threshold An upper thresholds to set
*
* \return Status of the ADC thresholds setting.
*/
int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* This function retrieves ADC threshold state.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[out] state The threshold state
*
* \return The state of ADC thresholds state retrieving.
*/
int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr,
adc_threshold_status_t *const state);
/**
* \brief Check if conversion is complete
*
* This function checks if the ADC has finished the conversion.
*
* \param[in] descr The pointer to the ADC descriptor
* \param[in] channel Channel number
*
* \return The status of ADC conversion completion checking.
* \retval 1 The conversion is complete
* \retval 0 The conversion is not complete
*/
int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t adc_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#include <hpl_missing_features.h>
#endif /* _HAL_ADC_SYNC_H_INCLUDED */

120
Smol Watch Project/My Project/hal/include/hal_atomic.h
View file

@ -1,120 +0,0 @@
/**
* \file
*
* \brief Critical sections related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_ATOMIC_H_INCLUDED
#define _HAL_ATOMIC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_atomic
*
*@{
*/
/**
* \brief Type for the register holding global interrupt enable flag
*/
typedef uint32_t hal_atomic_t;
/**
* \brief Helper macro for entering critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_enterCritical() function to enter critical
* sections. No semicolon is required after the macro.
*
* \section atomic_usage Usage Example
* \code
* CRITICAL_SECTION_ENTER()
* Critical code
* CRITICAL_SECTION_LEAVE()
* \endcode
*/
#define CRITICAL_SECTION_ENTER() \
{ \
volatile hal_atomic_t __atomic; \
atomic_enter_critical(&__atomic);
/**
* \brief Helper macro for leaving critical sections
*
* This macro is recommended to be used instead of a direct call
* hal_leaveCritical() function to leave critical
* sections. No semicolon is required after the macro.
*/
#define CRITICAL_SECTION_LEAVE() \
atomic_leave_critical(&__atomic); \
}
/**
* \brief Disable interrupts, enter critical section
*
* Disables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[out] atomic The pointer to a variable to store the value of global
* interrupt enable flag
*/
void atomic_enter_critical(hal_atomic_t volatile *atomic);
/**
* \brief Exit atomic section
*
* Enables global interrupts. Supports nested critical sections,
* so that global interrupts are only re-enabled
* upon leaving the outermost nested critical section.
*
* \param[in] atomic The pointer to a variable, which stores the latest stored
* value of the global interrupt enable flag
*/
void atomic_leave_critical(hal_atomic_t volatile *atomic);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t atomic_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_ATOMIC_H_INCLUDED */

159
Smol Watch Project/My Project/hal/include/hal_calendar.h
View file

@ -1,159 +0,0 @@
/**
* \file
*
* \brief Generic CALENDAR functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_CALENDER_H_INCLUDED
#define _HAL_CALENDER_H_INCLUDED
#include "hpl_calendar.h"
#include <utils_list.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_calendar_async
*
*@{
*/
/** \brief Prototype of callback on alarm match
* \param calendar Pointer to the HAL Calendar instance.
*/
typedef void (*calendar_cb_alarm_t)(struct calendar_descriptor *const calendar);
/** \brief Struct for alarm time
*/
struct calendar_alarm {
struct list_element elem;
struct _calendar_alarm cal_alarm;
calendar_cb_alarm_t callback;
};
/** \brief Initialize the Calendar HAL instance and hardware
*
* \param calendar Pointer to the HAL Calendar instance.
* \param hw Pointer to the hardware instance.
* \return Operation status of init
* \retval 0 Completed successfully.
*/
int32_t calendar_init(struct calendar_descriptor *const calendar, const void *hw);
/** \brief Reset the Calendar HAL instance and hardware
*
* Reset Calendar instance to hardware defaults.
*
* \param calendar Pointer to the HAL Calendar instance.
* \return Operation status of reset.
* \retval 0 Completed successfully.
*/
int32_t calendar_deinit(struct calendar_descriptor *const calendar);
/** \brief Enable the Calendar HAL instance and hardware
*
* \param calendar Pointer to the HAL Calendar instance.
* \return Operation status of init
* \retval 0 Completed successfully.
*/
int32_t calendar_enable(struct calendar_descriptor *const calendar);
/** \brief Disable the Calendar HAL instance and hardware
*
* Disable Calendar instance to hardware defaults.
*
* \param calendar Pointer to the HAL Calendar instance.
* \return Operation status of reset.
* \retval 0 Completed successfully.
*/
int32_t calendar_disable(struct calendar_descriptor *const calendar);
/** \brief Configure the base year for calendar HAL instance and hardware
*
* \param calendar Pointer to the HAL Calendar instance.
* \param p_base_year The desired base year.
* \retval 0 Completed successfully.
*/
int32_t calendar_set_baseyear(struct calendar_descriptor *const calendar, const uint32_t p_base_year);
/** \brief Configure the time for calendar HAL instance and hardware
*
* \param calendar Pointer to the HAL Calendar instance.
* \param p_calendar_time Pointer to the time configuration.
* \retval 0 Completed successfully.
*/
int32_t calendar_set_time(struct calendar_descriptor *const calendar, struct calendar_time *const p_calendar_time);
/** \brief Configure the date for calendar HAL instance and hardware
*
* \param calendar Pointer to the HAL Calendar instance.
* \param p_calendar_date Pointer to the date configuration.
* \return Operation status of time set.
* \retval 0 Completed successfully.
*/
int32_t calendar_set_date(struct calendar_descriptor *const calendar, struct calendar_date *const p_calendar_date);
/** \brief Get the time for calendar HAL instance and hardware
*
* \param calendar Pointer to the HAL Calendar instance.
* \param date_time Pointer to the value that will be filled with the current time.
* \return Operation status of time retrieve.
* \retval 0 Completed successfully.
*/
int32_t calendar_get_date_time(struct calendar_descriptor *const calendar, struct calendar_date_time *const date_time);
/** \brief Config the alarm time for calendar HAL instance and hardware
*
* Set the alarm time to calendar instance. If the callback is NULL, remove
* the alarm if the alarm is already added, otherwise, ignore the alarm.
*
* \param calendar Pointer to the HAL Calendar instance.
* \param alarm Pointer to the configuration.
* \param callback Pointer to the callback function.
* \return Operation status of alarm time set.
* \retval 0 Completed successfully.
*/
int32_t calendar_set_alarm(struct calendar_descriptor *const calendar, struct calendar_alarm *const alarm,
calendar_cb_alarm_t callback);
/** \brief Retrieve the current driver version
* \return Current driver version.
*/
uint32_t calendar_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_CALENDER_H_INCLUDED */

89
Smol Watch Project/My Project/hal/include/hal_delay.h
View file

@ -1,89 +0,0 @@
/**
* \file
*
* \brief HAL delay related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_irq.h>
#include <hpl_reset.h>
#include <hpl_sleep.h>
#ifndef _HAL_DELAY_H_INCLUDED
#define _HAL_DELAY_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_delay Delay Driver
*
*@{
*/
/**
* \brief Initialize Delay driver
*
* \param[in] hw The pointer to hardware instance
*/
void delay_init(void *const hw);
/**
* \brief Perform delay in us
*
* This function performs delay for the given amount of microseconds.
*
* \param[in] us The amount delay in us
*/
void delay_us(const uint16_t us);
/**
* \brief Perform delay in ms
*
* This function performs delay for the given amount of milliseconds.
*
* \param[in] ms The amount delay in ms
*/
void delay_ms(const uint16_t ms);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t delay_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_DELAY_H_INCLUDED */

118
Smol Watch Project/My Project/hal/include/hal_ext_irq.h
View file

@ -1,118 +0,0 @@
/**
* \file
*
* \brief External interrupt functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_EXT_IRQ_H_INCLUDED
#define _HAL_EXT_IRQ_H_INCLUDED
#include <hpl_ext_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_ext_irq
*
* @{
*/
/**
* \brief External IRQ callback type
*/
typedef void (*ext_irq_cb_t)(void);
/**
* \brief Initialize external IRQ component, if any
*
* \return Initialization status.
* \retval -1 External IRQ module is already initialized
* \retval 0 The initialization is completed successfully
*/
int32_t ext_irq_init(void);
/**
* \brief Deinitialize external IRQ, if any
*
* \return De-initialization status.
* \retval -1 External IRQ module is already deinitialized
* \retval 0 The de-initialization is completed successfully
*/
int32_t ext_irq_deinit(void);
/**
* \brief Register callback for the given external interrupt
*
* \param[in] pin Pin to enable external IRQ on
* \param[in] cb Callback function
*
* \return Registration status.
* \retval -1 Passed parameters were invalid
* \retval 0 The callback registration is completed successfully
*/
int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb);
/**
* \brief Enable external IRQ
*
* \param[in] pin Pin to enable external IRQ on
*
* \return Enabling status.
* \retval -1 Passed parameters were invalid
* \retval 0 The enabling is completed successfully
*/
int32_t ext_irq_enable(const uint32_t pin);
/**
* \brief Disable external IRQ
*
* \param[in] pin Pin to enable external IRQ on
*
* \return Disabling status.
* \retval -1 Passed parameters were invalid
* \retval 0 The disabling is completed successfully
*/
int32_t ext_irq_disable(const uint32_t pin);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t ext_irq_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_EXT_IRQ_H_INCLUDED */

201
Smol Watch Project/My Project/hal/include/hal_gpio.h
View file

@ -1,201 +0,0 @@
/**
* \file
*
* \brief Port
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*/
#ifndef _HAL_GPIO_INCLUDED_
#define _HAL_GPIO_INCLUDED_
#include <hpl_gpio.h>
#include <utils_assert.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Set gpio pull mode
*
* Set pin pull mode, non existing pull modes throws an fatal assert
*
* \param[in] pin The pin number for device
* \param[in] pull_mode GPIO_PULL_DOWN = Pull pin low with internal resistor
* GPIO_PULL_UP = Pull pin high with internal resistor
* GPIO_PULL_OFF = Disable pin pull mode
*/
static inline void gpio_set_pin_pull_mode(const uint8_t pin, const enum gpio_pull_mode pull_mode)
{
_gpio_set_pin_pull_mode((enum gpio_port)GPIO_PORT(pin), pin & 0x1F, pull_mode);
}
/**
* \brief Set pin function
*
* Select which function a pin will be used for
*
* \param[in] pin The pin number for device
* \param[in] function The pin function is given by a 32-bit wide bitfield
* found in the header files for the device
*
*/
static inline void gpio_set_pin_function(const uint32_t pin, uint32_t function)
{
_gpio_set_pin_function(pin, function);
}
/**
* \brief Set port data direction
*
* Select if the pin data direction is input, output or disabled.
* If disabled state is not possible, this function throws an assert.
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to the
* corresponding pin
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
* GPIO_DIRECTION_OUT = Data direction out
* GPIO_DIRECTION_OFF = Disables the pin
* (low power state)
*/
static inline void gpio_set_port_direction(const enum gpio_port port, const uint32_t mask,
const enum gpio_direction direction)
{
_gpio_set_direction(port, mask, direction);
}
/**
* \brief Set gpio data direction
*
* Select if the pin data direction is input, output or disabled.
* If disabled state is not possible, this function throws an assert.
*
* \param[in] pin The pin number for device
* \param[in] direction GPIO_DIRECTION_IN = Data direction in
* GPIO_DIRECTION_OUT = Data direction out
* GPIO_DIRECTION_OFF = Disables the pin
* (low power state)
*/
static inline void gpio_set_pin_direction(const uint8_t pin, const enum gpio_direction direction)
{
_gpio_set_direction((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), direction);
}
/**
* \brief Set port level
*
* Sets output level on the pins defined by the bit mask
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply port level to the corresponding
* pin
* \param[in] level true = Pin levels set to "high" state
* false = Pin levels set to "low" state
*/
static inline void gpio_set_port_level(const enum gpio_port port, const uint32_t mask, const bool level)
{
_gpio_set_level(port, mask, level);
}
/**
* \brief Set gpio level
*
* Sets output level on a pin
*
* \param[in] pin The pin number for device
* \param[in] level true = Pin level set to "high" state
* false = Pin level set to "low" state
*/
static inline void gpio_set_pin_level(const uint8_t pin, const bool level)
{
_gpio_set_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin), level);
}
/**
* \brief Toggle out level on pins
*
* Toggle the pin levels on pins defined by bit mask
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means toggle pin level to the corresponding
* pin
*/
static inline void gpio_toggle_port_level(const enum gpio_port port, const uint32_t mask)
{
_gpio_toggle_level(port, mask);
}
/**
* \brief Toggle output level on pin
*
* Toggle the pin levels on pins defined by bit mask
*
* \param[in] pin The pin number for device
*/
static inline void gpio_toggle_pin_level(const uint8_t pin)
{
_gpio_toggle_level((enum gpio_port)GPIO_PORT(pin), 1U << GPIO_PIN(pin));
}
/**
* \brief Get input level on pins
*
* Read the input level on pins connected to a port
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
*/
static inline uint32_t gpio_get_port_level(const enum gpio_port port)
{
return _gpio_get_level(port);
}
/**
* \brief Get level on pin
*
* Reads the level on pins connected to a port
*
* \param[in] pin The pin number for device
*/
static inline bool gpio_get_pin_level(const uint8_t pin)
{
return (bool)(_gpio_get_level((enum gpio_port)GPIO_PORT(pin)) & (0x01U << GPIO_PIN(pin)));
}
/**
* \brief Get current driver version
*/
uint32_t gpio_get_version(void);
#ifdef __cplusplus
}
#endif
#endif

244
Smol Watch Project/My Project/hal/include/hal_i2c_m_sync.h
View file

@ -1,244 +0,0 @@
/**
* \file
*
* \brief Sync I2C Hardware Abstraction Layer(HAL) declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_I2C_M_SYNC_H_INCLUDED
#define _HAL_I2C_M_SYNC_H_INCLUDED
#include <hpl_i2c_m_sync.h>
#include <hal_io.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_i2c_master_sync
*
* @{
*/
#define I2C_M_MAX_RETRY 1
/**
* \brief I2C descriptor structure, embed i2c_device & i2c_interface
*/
struct i2c_m_sync_desc {
struct _i2c_m_sync_device device;
struct io_descriptor io;
uint16_t slave_addr;
};
/**
* \brief Initialize synchronous I2C interface
*
* This function initializes the given I/O descriptor to be used as a
* synchronous I2C interface descriptor.
* It checks if the given hardware is not initialized and if the given hardware
* is permitted to be initialized.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status.
* \retval -1 The passed parameters were invalid or the interface is already initialized
* \retval 0 The initialization is completed successfully
*/
int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw);
/**
* \brief Deinitialize I2C interface
*
* This function deinitializes the given I/O descriptor.
* It checks if the given hardware is initialized and if the given hardware is permitted to be deinitialized.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return Uninitialization status.
* \retval -1 The passed parameters were invalid or the interface is already deinitialized
* \retval 0 The de-initialization is completed successfully
*/
int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c);
/**
* \brief Set the slave device address
*
* This function sets the next transfer target slave I2C device address.
* It takes no effect to any already started access.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] addr The slave address to access
* \param[in] addr_len The slave address length, can be I2C_M_TEN or I2C_M_SEVEN
*
* \return Masked slave address. The mask is a maximum 10-bit address, and 10th
* bit is set if a 10-bit address is used
*/
int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len);
/**
* \brief Set baudrate
*
* This function sets the I2C device to the specified baudrate.
* It only takes effect when the hardware is disabled.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] clkrate Unused parameter. Should always be 0
* \param[in] baudrate The baudrate value set to master
*
* \return Whether successfully set the baudrate
* \retval -1 The passed parameters were invalid or the device is already enabled
* \retval 0 The baudrate set is completed successfully
*/
int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate);
/**
* \brief Sync version of enable hardware
*
* This function enables the I2C device, and then waits for this enabling operation to be done
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return Whether successfully enable the device
* \retval -1 The passed parameters were invalid or the device enable failed
* \retval 0 The hardware enabling is completed successfully
*/
int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c);
/**
* \brief Sync version of disable hardware
*
* This function disables the I2C device and then waits for this disabling operation to be done
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return Whether successfully disable the device
* \retval -1 The passed parameters were invalid or the device disable failed
* \retval 0 The hardware disabling is completed successfully
*/
int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c);
/**
* \brief Sync version of write command to I2C slave
*
* This function will write the value to a specified register in the I2C slave device and
* then wait for this operation to be done.
*
* The sequence of this routine is
* sta->address(write)->ack->reg address->ack->resta->address(write)->ack->reg value->nack->stt
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] reg The internal address/register of the I2C slave device
* \param[in] buffer The buffer holding data to write to the I2C slave device
* \param[in] length The length (in bytes) to write to the I2C slave device
*
* \return Whether successfully write to the device
* \retval <0 The passed parameters were invalid or write fail
* \retval 0 Writing to register is completed successfully
*/
int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
/**
* \brief Sync version of read register value from I2C slave
*
* This function will read a byte value from a specified register in the I2C slave device and
* then wait for this operation to be done.
*
* The sequence of this routine is
* sta->address(write)->ack->reg address->ack->resta->address(read)->ack->reg value->nack->stt
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] reg The internal address/register of the I2C slave device
* \param[in] buffer The buffer to hold the read data from the I2C slave device
* \param[in] length The length (in bytes) to read from the I2C slave device
*
* \return Whether successfully read from the device
* \retval <0 The passed parameters were invalid or read fail
* \retval 0 Reading from register is completed successfully
*/
int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length);
/**
* \brief Sync version of transfer message to/from the I2C slave
*
* This function will transfer a message between the I2C slave and the master. This function will wait for the operation
* to be done.
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
* \param[in] msg An i2c_m_msg struct
*
* \return The status of the operation
* \retval 0 Operation completed successfully
* \retval <0 Operation failed
*/
int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg);
/**
* \brief Sync version of send stop condition on the i2c bus
*
* This function will create a stop condition on the i2c bus to release the bus
*
* \param[in] i2c An I2C descriptor, which is used to communicate through I2C
*
* \return The status of the operation
* \retval 0 Operation completed successfully
* \retval <0 Operation failed
*/
int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c);
/**
* \brief Return I/O descriptor for this I2C instance
*
* This function will return a I/O instance for this I2C driver instance
*
* \param[in] i2c_m_sync_desc An I2C descriptor, which is used to communicate through I2C
* \param[in] io_descriptor A pointer to an I/O descriptor pointer type
*
* \return Error code
* \retval 0 No error detected
* \retval <0 Error code
*/
int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t i2c_m_sync_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

72
Smol Watch Project/My Project/hal/include/hal_init.h
View file

@ -1,72 +0,0 @@
/**
* \file
*
* \brief HAL initialization related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_INIT_H_INCLUDED
#define _HAL_INIT_H_INCLUDED
#include <hpl_init.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_init Init Driver
*
*@{
*/
/**
* \brief Initialize the hardware abstraction layer
*
* This function calls the various initialization functions.
* Currently the following initialization functions are supported:
* - System clock initialization
*/
static inline void init_mcu(void)
{
_init_chip();
}
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t init_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_INIT_H_INCLUDED */

110
Smol Watch Project/My Project/hal/include/hal_io.h
View file

@ -1,110 +0,0 @@
/**
* \file
*
* \brief I/O related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_IO_INCLUDED
#define _HAL_IO_INCLUDED
/**
* \addtogroup doc_driver_hal_helper_io I/O Driver
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief I/O descriptor
*
* The I/O descriptor forward declaration.
*/
struct io_descriptor;
/**
* \brief I/O write function pointer type
*/
typedef int32_t (*io_write_t)(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
/**
* \brief I/O read function pointer type
*/
typedef int32_t (*io_read_t)(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
/**
* \brief I/O descriptor
*/
struct io_descriptor {
io_write_t write; /*! The write function pointer. */
io_read_t read; /*! The read function pointer. */
};
/**
* \brief I/O write interface
*
* This function writes up to \p length of bytes to a given I/O descriptor.
* It returns the number of bytes actually write.
*
* \param[in] descr An I/O descriptor to write
* \param[in] buf The buffer pointer to story the write data
* \param[in] length The number of bytes to write
*
* \return The number of bytes written
*/
int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length);
/**
* \brief I/O read interface
*
* This function reads up to \p length bytes from a given I/O descriptor, and
* stores it in the buffer pointed to by \p buf. It returns the number of bytes
* actually read.
*
* \param[in] descr An I/O descriptor to read
* \param[in] buf The buffer pointer to story the read data
* \param[in] length The number of bytes to read
*
* \return The number of bytes actually read. This number can be less than the
* requested length. E.g., in a driver that uses ring buffer for
* reception, it may depend on the availability of data in the
* ring buffer.
*/
int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HAL_IO_INCLUDED */

151
Smol Watch Project/My Project/hal/include/hal_pwm.h
View file

@ -1,151 +0,0 @@
/**
* \file
*
* \brief PWM functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef HAL_PWM_H_INCLUDED
#define HAL_PWM_H_INCLUDED
#include <hpl_pwm.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_pwm_async
*
*@{
*/
/**
* \brief PWM descriptor
*
* The PWM descriptor forward declaration.
*/
struct pwm_descriptor;
/**
* \brief PWM callback type
*/
typedef void (*pwm_cb_t)(const struct pwm_descriptor *const descr);
/**
* \brief PWM callback types
*/
enum pwm_callback_type { PWM_PERIOD_CB, PWM_ERROR_CB };
/**
* \brief PWM callbacks
*/
struct pwm_callbacks {
pwm_cb_t period;
pwm_cb_t error;
};
/** \brief PWM descriptor
*/
struct pwm_descriptor {
/** PWM device */
struct _pwm_device device;
/** PWM callback structure */
struct pwm_callbacks pwm_cb;
};
/** \brief Initialize the PWM HAL instance and hardware
*
* \param[in] descr Pointer to the HAL PWM descriptor
* \param[in] hw The pointer to hardware instance
* \param[in] func The pointer to a set of functions pointers
*
* \return Operation status.
*/
int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func);
/** \brief Deinitialize the PWM HAL instance and hardware
*
* \param[in] descr Pointer to the HAL PWM descriptor
*
* \return Operation status.
*/
int32_t pwm_deinit(struct pwm_descriptor *const descr);
/** \brief PWM output start
*
* \param[in] descr Pointer to the HAL PWM descriptor
*
* \return Operation status.
*/
int32_t pwm_enable(struct pwm_descriptor *const descr);
/** \brief PWM output stop
*
* \param[in] descr Pointer to the HAL PWM descriptor
*
* \return Operation status.
*/
int32_t pwm_disable(struct pwm_descriptor *const descr);
/** \brief Register PWM callback
*
* \param[in] descr Pointer to the HAL PWM descriptor
* \param[in] type Callback type
* \param[in] cb A callback function, passing NULL de-registers callback
*
* \return Operation status.
* \retval 0 Success
* \retval -1 Error
*/
int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb);
/** \brief Change PWM parameter
*
* \param[in] descr Pointer to the HAL PWM descriptor
* \param[in] period Total period of one PWM cycle
* \param[in] duty_cycle Period of PWM first half during one cycle
*
* \return Operation status.
*/
int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period,
const pwm_period_t duty_cycle);
/** \brief Get PWM driver version
*
* \return Current driver version.
*/
uint32_t pwm_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* HAL_PWM;_H_INCLUDED */

168
Smol Watch Project/My Project/hal/include/hal_slcd_sync.h
View file

@ -1,168 +0,0 @@
/**
* \file
*
* \brief SLCD Segment Liquid Crystal Display Controller(Sync) functionality
* declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef HAL_SLCD_SYNC_H_INCLUDED
#define HAL_SLCD_SYNC_H_INCLUDED
#include <hpl_slcd_sync.h>
#include <utils_assert.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_slcd_sync
*
*@{
*/
struct slcd_sync_descriptor {
struct _slcd_sync_device dev; /*!< SLCD HPL device descriptor */
};
/**
* \brief Initialize SLCD Descriptor
*
* \param[in] descr SLCD descriptor to be initialized
* \param[in] hw The pointer to hardware instance
*/
int32_t slcd_sync_init(struct slcd_sync_descriptor *const descr, void *const hw);
/**
* \brief Deinitialize SLCD Descriptor
*
* \param[in] descr SLCD descriptor to be deinitialized
*/
int32_t slcd_sync_deinit(struct slcd_sync_descriptor *const descr);
/**
* \brief Enable SLCD driver
*
* \param[in] descr SLCD descriptor to be initialized
*/
int32_t slcd_sync_enable(struct slcd_sync_descriptor *const descr);
/**
* \brief Disable SLCD driver
*
* \param[in] descr SLCD descriptor to be disabled
*/
int32_t slcd_sync_disable(struct slcd_sync_descriptor *const descr);
/**
* \brief Turn on a Segment
*
* \param[in] descr SLCD descriptor to be enabled
* \param[in] seg Segment index. The segment index is by the combination
* of common and segment terminal index. The
* SLCD_SEGID(com, seg) macro can generate the index.
*/
int32_t slcd_sync_seg_on(struct slcd_sync_descriptor *const descr, uint32_t seg);
/**
* \brief Turn off a Segment
*
* \param[in] descr SLCD descriptor
* \param[in] seg Segment index
* value is "(common terminals << 16 | segment terminal)"
*/
int32_t slcd_sync_seg_off(struct slcd_sync_descriptor *const descr, uint32_t seg);
/**
* \brief Blink a Segment
*
* \param[in] descr SLCD descriptor
* \param[in] seg Segment index
* value is "(common terminals << 16 | segment terminal)"
* \param[in] period Blink period, unit is millisecond
*/
int32_t slcd_sync_seg_blink(struct slcd_sync_descriptor *const descr, uint32_t seg, const uint32_t period);
/**
* \brief Displays a character
*
* \param[in] descr SLCD descriptor
* \param[in] character Character to be displayed
* \param[in] index Index of the character Mapping Group
*/
int32_t slcd_sync_write_char(struct slcd_sync_descriptor *const descr, const uint8_t character, uint32_t index);
/**
* \brief Displays character string string
*
* \param[in] descr SLCD descriptor
* \param[in] str String to be displayed, 0 will turn off the
* corresponding char to display
* \param[in] len Length of the string array
* \param[in] index Index of the character Mapping Group
*/
int32_t slcd_sync_write_string(struct slcd_sync_descriptor *const descr, uint8_t *const str, uint32_t len,
uint32_t index);
/**
* \brief Start animation play by a segment array
*
* \param[in] descr SLCD descriptor
* \param[in] segs Segment array
* \param[in] len Length of the segment array
* \param[in] period Period (milliseconds) of each segment to animation
*/
int32_t slcd_sync_start_animation(struct slcd_sync_descriptor *const descr, const uint32_t segs[], uint32_t len,
const uint32_t period);
/**
* \brief Stop animation play by a segment array
*
* \param[in] descr SLCD descriptor
* \param[in] segs Segment array
* \param[in] len Length of the segment array
*/
int32_t slcd_sync_stop_animation(struct slcd_sync_descriptor *const descr, const uint32_t segs[], uint32_t len);
/**
* \brief Set animation Frequency
*
* \param[in] descr SLCD descriptor
* \param[in] period Period (million second) of each segment to animation
*/
int32_t slcd_sync_set_animation_period(struct slcd_sync_descriptor *const descr, const uint32_t period);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif

74
Smol Watch Project/My Project/hal/include/hal_sleep.h
View file

@ -1,74 +0,0 @@
/**
* \file
*
* \brief Sleep related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HAL_SLEEP_H_INCLUDED
#define _HAL_SLEEP_H_INCLUDED
#include <hpl_sleep.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \addtogroup doc_driver_hal_helper_sleep
*
*@{
*/
/**
* \brief Set the sleep mode of the device and put the MCU to sleep
*
* For an overview of which systems are disabled in sleep for the different
* sleep modes, see the data sheet.
*
* \param[in] mode Sleep mode to use
*
* \return The status of a sleep request
* \retval -1 The requested sleep mode was invalid or not available
* \retval 0 The operation completed successfully, returned after leaving the
* sleep
*/
int sleep(const uint8_t mode);
/**
* \brief Retrieve the current driver version
*
* \return Current driver version.
*/
uint32_t sleep_get_version(void);
/**@}*/
#ifdef __cplusplus
}
#endif
#endif /* _HAL_SLEEP_H_INCLUDED */

264
Smol Watch Project/My Project/hal/include/hpl_adc_async.h
View file

@ -1,264 +0,0 @@
/**
* \file
*
* \brief ADC related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_ADC_ASYNC_H_INCLUDED
#define _HPL_ADC_ASYNC_H_INCLUDED
/**
* \addtogroup HPL ADC
*
* \section hpl_async_adc_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "hpl_adc_sync.h"
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief ADC device structure
*
* The ADC device structure forward declaration.
*/
struct _adc_async_device;
/**
* \brief ADC callback types
*/
enum _adc_async_callback_type { ADC_ASYNC_DEVICE_CONVERT_CB, ADC_ASYNC_DEVICE_MONITOR_CB, ADC_ASYNC_DEVICE_ERROR_CB };
/**
* \brief ADC interrupt callbacks
*/
struct _adc_async_callbacks {
void (*window_cb)(struct _adc_async_device *device, const uint8_t channel);
void (*error_cb)(struct _adc_async_device *device, const uint8_t channel);
};
/**
* \brief ADC channel interrupt callbacks
*/
struct _adc_async_ch_callbacks {
void (*convert_done)(struct _adc_async_device *device, const uint8_t channel, const uint16_t data);
};
/**
* \brief ADC descriptor device structure
*/
struct _adc_async_device {
struct _adc_async_callbacks adc_async_cb;
struct _adc_async_ch_callbacks adc_async_ch_cb;
struct _irq_descriptor irq;
void * hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize synchronous ADC
*
* This function does low level ADC configuration.
*
* param[in] device The pointer to ADC device instance
* param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _adc_async_init(struct _adc_async_device *const device, void *const hw);
/**
* \brief Deinitialize ADC
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_async_deinit(struct _adc_async_device *const device);
/**
* \brief Enable ADC peripheral
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_async_enable_channel(struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Disable ADC peripheral
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_async_disable_channel(struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Retrieve ADC conversion data size
*
* \param[in] device The pointer to ADC device instance
*
* \return The data size in bytes
*/
uint8_t _adc_async_get_data_size(const struct _adc_async_device *const device);
/**
* \brief Check if conversion is done
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* \return The status of conversion
* \retval true The conversion is done
* \retval false The conversion is not done
*/
bool _adc_async_is_channel_conversion_done(const struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Make conversion
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_async_convert(struct _adc_async_device *const device);
/**
* \brief Retrieve the conversion result
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* The result value
*/
uint16_t _adc_async_read_channel_data(const struct _adc_async_device *const device, const uint8_t channel);
/**
* \brief Set reference source
*
* \param[in] device The pointer to ADC device instance
* \param[in] reference A reference source to set
*/
void _adc_async_set_reference_source(struct _adc_async_device *const device, const adc_reference_t reference);
/**
* \brief Set resolution
*
* \param[in] device The pointer to ADC device instance
* \param[in] resolution A resolution to set
*/
void _adc_async_set_resolution(struct _adc_async_device *const device, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* \param[in] device The pointer to ADC device instance
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*/
void _adc_async_set_inputs(struct _adc_async_device *const device, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set conversion mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A conversion mode to set
*/
void _adc_async_set_conversion_mode(struct _adc_async_device *const device, const enum adc_conversion_mode mode);
/**
* \brief Set differential mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*/
void _adc_async_set_channel_differential_mode(struct _adc_async_device *const device, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set gain
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] gain A gain to set
*/
void _adc_async_set_channel_gain(struct _adc_async_device *const device, const uint8_t channel, const adc_gain_t gain);
/**
* \brief Set window mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A mode to set
*/
void _adc_async_set_window_mode(struct _adc_async_device *const device, const adc_window_mode_t mode);
/**
* \brief Set lower threshold
*
* \param[in] device The pointer to ADC device instance
* \param[in] low_threshold A lower threshold to set
* \param[in] up_threshold An upper thresholds to set
*/
void _adc_async_set_thresholds(struct _adc_async_device *const device, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* \param[in] device The pointer to ADC device instance
* \param[out] state The threshold state
*/
void _adc_async_get_threshold_state(const struct _adc_async_device *const device, adc_threshold_status_t *const state);
/**
* \brief Enable/disable ADC channel interrupt
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] type The type of interrupt to disable/enable if applicable
* \param[in] state Enable or disable
*/
void _adc_async_set_irq_state(struct _adc_async_device *const device, const uint8_t channel,
const enum _adc_async_callback_type type, const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_ADC_ASYNC_H_INCLUDED */

243
Smol Watch Project/My Project/hal/include/hpl_adc_dma.h
View file

@ -1,243 +0,0 @@
/**
* \file
*
* \brief ADC related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_ADC_DMA_H_INCLUDED
#define _HPL_ADC_DMA_H_INCLUDED
/**
* \addtogroup HPL ADC
*
* \section hpl_dma_adc_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <hpl_adc_sync.h>
#include <hpl_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief ADC device structure
*
* The ADC device structure forward declaration.
*/
struct _adc_dma_device;
/**
* \brief ADC callback types
*/
enum _adc_dma_callback_type { ADC_DMA_DEVICE_COMPLETE_CB, ADC_DMA_DEVICE_ERROR_CB };
/**
* \brief ADC interrupt callbacks
*/
struct _adc_dma_callbacks {
void (*complete)(struct _adc_dma_device *device, const uint16_t data);
void (*error)(struct _adc_dma_device *device);
};
/**
* \brief ADC descriptor device structure
*/
struct _adc_dma_device {
struct _adc_dma_callbacks adc_dma_cb;
struct _irq_descriptor irq;
void * hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize synchronous ADC
*
* This function does low level ADC configuration.
*
* param[in] device The pointer to ADC device instance
* param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _adc_dma_init(struct _adc_dma_device *const device, void *const hw);
/**
* \brief Deinitialize ADC
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_dma_deinit(struct _adc_dma_device *const device);
/**
* \brief Enable ADC peripheral
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_dma_enable_channel(struct _adc_dma_device *const device, const uint8_t channel);
/**
* \brief Disable ADC peripheral
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_dma_disable_channel(struct _adc_dma_device *const device, const uint8_t channel);
/**
* \brief Return address of ADC DMA source
*
* \param[in] device The pointer to ADC device instance
*
* \return ADC DMA source address
*/
uint32_t _adc_get_source_for_dma(struct _adc_dma_device *const device);
/**
* \brief Retrieve ADC conversion data size
*
* \param[in] device The pointer to ADC device instance
*
* \return The data size in bytes
*/
uint8_t _adc_dma_get_data_size(const struct _adc_dma_device *const device);
/**
* \brief Check if conversion is done
*
* \param[in] device The pointer to ADC device instance
*
* \return The status of conversion
* \retval true The conversion is done
* \retval false The conversion is not done
*/
bool _adc_dma_is_conversion_done(const struct _adc_dma_device *const device);
/**
* \brief Make conversion
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_dma_convert(struct _adc_dma_device *const device);
/**
* \brief Set reference source
*
* \param[in] device The pointer to ADC device instance
* \param[in] reference A reference source to set
*/
void _adc_dma_set_reference_source(struct _adc_dma_device *const device, const adc_reference_t reference);
/**
* \brief Set resolution
*
* \param[in] device The pointer to ADC device instance
* \param[in] resolution A resolution to set
*/
void _adc_dma_set_resolution(struct _adc_dma_device *const device, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* \param[in] device The pointer to ADC device instance
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*/
void _adc_dma_set_inputs(struct _adc_dma_device *const device, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set conversion mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A conversion mode to set
*/
void _adc_dma_set_conversion_mode(struct _adc_dma_device *const device, const enum adc_conversion_mode mode);
/**
* \brief Set differential mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*/
void _adc_dma_set_channel_differential_mode(struct _adc_dma_device *const device, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set gain
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] gain A gain to set
*/
void _adc_dma_set_channel_gain(struct _adc_dma_device *const device, const uint8_t channel, const adc_gain_t gain);
/**
* \brief Set window mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A mode to set
*/
void _adc_dma_set_window_mode(struct _adc_dma_device *const device, const adc_window_mode_t mode);
/**
* \brief Set thresholds
*
* \param[in] device The pointer to ADC device instance
* \param[in] low_threshold A lower thresholds to set
* \param[in] up_threshold An upper thresholds to set
*/
void _adc_dma_set_thresholds(struct _adc_dma_device *const device, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* \param[in] device The pointer to ADC device instance
* \param[out] state The threshold state
*/
void _adc_dma_get_threshold_state(const struct _adc_dma_device *const device, adc_threshold_status_t *const state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_ADC_DMA_H_INCLUDED */

271
Smol Watch Project/My Project/hal/include/hpl_adc_sync.h
View file

@ -1,271 +0,0 @@
/**
* \file
*
* \brief ADC related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_ADC_SYNC_H_INCLUDED
#define _HPL_ADC_SYNC_H_INCLUDED
/**
* \addtogroup HPL ADC
*
* \section hpl_adc_sync_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "compiler.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief ADC reference source
*/
typedef uint8_t adc_reference_t;
/**
* \brief ADC resolution
*/
typedef uint8_t adc_resolution_t;
/**
* \brief ADC positive input for channel
*/
typedef uint8_t adc_pos_input_t;
/**
* \brief ADC negative input for channel
*/
typedef uint8_t adc_neg_input_t;
/**
* \brief ADC threshold
*/
typedef uint16_t adc_threshold_t;
/**
* \brief ADC gain
*/
typedef uint8_t adc_gain_t;
/**
* \brief ADC conversion mode
*/
enum adc_conversion_mode { ADC_CONVERSION_MODE_SINGLE_CONVERSION = 0, ADC_CONVERSION_MODE_FREERUN };
/**
* \brief ADC differential mode
*/
enum adc_differential_mode { ADC_DIFFERENTIAL_MODE_SINGLE_ENDED = 0, ADC_DIFFERENTIAL_MODE_DIFFERENTIAL };
/**
* \brief ADC window mode
*/
typedef uint8_t adc_window_mode_t;
/**
* \brief ADC threshold status
*/
typedef bool adc_threshold_status_t;
/**
* \brief ADC sync descriptor device structure
*/
struct _adc_sync_device {
void *hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize synchronous ADC
*
* This function does low level ADC configuration.
*
* param[in] device The pointer to ADC device instance
* param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _adc_sync_init(struct _adc_sync_device *const device, void *const hw);
/**
* \brief Deinitialize ADC
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_sync_deinit(struct _adc_sync_device *const device);
/**
* \brief Enable ADC
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_sync_enable_channel(struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Disable ADC
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*/
void _adc_sync_disable_channel(struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Retrieve ADC conversion data size
*
* \param[in] device The pointer to ADC device instance
*
* \return The data size in bytes
*/
uint8_t _adc_sync_get_data_size(const struct _adc_sync_device *const device);
/**
* \brief Check if conversion is done
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* \return The status of conversion
* \retval true The conversion is done
* \retval false The conversion is not done
*/
bool _adc_sync_is_channel_conversion_done(const struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Make conversion
*
* \param[in] device The pointer to ADC device instance
*/
void _adc_sync_convert(struct _adc_sync_device *const device);
/**
* \brief Retrieve the conversion result
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
*
* \return The result value of channel
*/
uint16_t _adc_sync_read_channel_data(const struct _adc_sync_device *const device, const uint8_t channel);
/**
* \brief Set reference source
*
* \param[in] device The pointer to ADC device instance
* \param[in] reference A reference source to set
*/
void _adc_sync_set_reference_source(struct _adc_sync_device *const device, const adc_reference_t reference);
/**
* \brief Set resolution
*
* \param[in] device The pointer to ADC device instance
* \param[in] resolution A resolution to set
*/
void _adc_sync_set_resolution(struct _adc_sync_device *const device, const adc_resolution_t resolution);
/**
* \brief Set ADC input source of a channel
*
* \param[in] device The pointer to ADC device instance
* \param[in] pos_input A positive input source to set
* \param[in] neg_input A negative input source to set
* \param[in] channel Channel number
*/
void _adc_sync_set_inputs(struct _adc_sync_device *const device, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel);
/**
* \brief Set conversion mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A conversion mode to set
*/
void _adc_sync_set_conversion_mode(struct _adc_sync_device *const device, const enum adc_conversion_mode mode);
/**
* \brief Set differential mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] mode A differential mode to set
*/
void _adc_sync_set_channel_differential_mode(struct _adc_sync_device *const device, const uint8_t channel,
const enum adc_differential_mode mode);
/**
* \brief Set gain
*
* \param[in] device The pointer to ADC device instance
* \param[in] channel Channel number
* \param[in] gain A gain to set
*/
void _adc_sync_set_channel_gain(struct _adc_sync_device *const device, const uint8_t channel, const adc_gain_t gain);
/**
* \brief Set window mode
*
* \param[in] device The pointer to ADC device instance
* \param[in] mode A mode to set
*/
void _adc_sync_set_window_mode(struct _adc_sync_device *const device, const adc_window_mode_t mode);
/**
* \brief Set threshold
*
* \param[in] device The pointer to ADC device instance
* \param[in] low_threshold A lower threshold to set
* \param[in] up_threshold An upper thresholds to set
*/
void _adc_sync_set_thresholds(struct _adc_sync_device *const device, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold);
/**
* \brief Retrieve threshold state
*
* \param[in] device The pointer to ADC device instance
* \param[out] state The threshold state
*/
void _adc_sync_get_threshold_state(const struct _adc_sync_device *const device, adc_threshold_status_t *const state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_ADC_SYNC_H_INCLUDED */

318
Smol Watch Project/My Project/hal/include/hpl_calendar.h
View file

@ -1,318 +0,0 @@
/**
* \file
*
* \brief Generic CALENDAR functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_CALENDER_H_INCLUDED
#define _HPL_CALENDER_H_INCLUDED
#include <compiler.h>
#include <utils_list.h>
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Calendar structure
*
* The Calendar structure forward declaration.
*/
struct calendar_dev;
/**
* \brief Available mask options for alarms.
*
* Available mask options for alarms.
*/
enum calendar_alarm_option {
/** Alarm disabled. */
CALENDAR_ALARM_MATCH_DISABLED = 0,
/** Alarm match on second. */
CALENDAR_ALARM_MATCH_SEC,
/** Alarm match on second and minute. */
CALENDAR_ALARM_MATCH_MIN,
/** Alarm match on second, minute, and hour. */
CALENDAR_ALARM_MATCH_HOUR,
/** Alarm match on second, minute, hour, and day. */
CALENDAR_ALARM_MATCH_DAY,
/** Alarm match on second, minute, hour, day, and month. */
CALENDAR_ALARM_MATCH_MONTH,
/** Alarm match on second, minute, hour, day, month and year. */
CALENDAR_ALARM_MATCH_YEAR
};
/**
* \brief Available mode for alarms.
*/
enum calendar_alarm_mode { ONESHOT = 1, REPEAT };
/**
* \brief Prototype of callback on alarm match
*/
typedef void (*calendar_drv_cb_alarm_t)(struct calendar_dev *const dev);
/**
* \brief Prototype of callback on tamper detect
*/
typedef void (*tamper_drv_cb_t)(struct calendar_dev *const dev);
/**
* \brief Structure of Calendar instance
*/
struct calendar_dev {
/** Pointer to the hardware base */
void *hw;
/** Alarm match callback */
calendar_drv_cb_alarm_t callback;
/** Tamper callback */
tamper_drv_cb_t callback_tamper;
/** IRQ struct */
struct _irq_descriptor irq;
};
/**
* \brief Time struct for calendar
*/
struct calendar_time {
/*range from 0 to 59*/
uint8_t sec;
/*range from 0 to 59*/
uint8_t min;
/*range from 0 to 23*/
uint8_t hour;
};
/**
* \brief Time struct for calendar
*/
struct calendar_date {
/*range from 1 to 28/29/30/31*/
uint8_t day;
/*range from 1 to 12*/
uint8_t month;
/*absolute year>= 1970(such as 2000)*/
uint16_t year;
};
/** \brief Calendar driver struct
*
*/
struct calendar_descriptor {
struct calendar_dev device;
struct list_descriptor alarms;
/*base date/time = base_year/1/1/0/0/0(year/month/day/hour/min/sec)*/
uint32_t base_year;
uint8_t flags;
};
/** \brief Date&Time struct for calendar
*/
struct calendar_date_time {
struct calendar_time time;
struct calendar_date date;
};
/** \brief struct for alarm time
*/
struct _calendar_alarm {
struct calendar_date_time datetime;
uint32_t timestamp;
enum calendar_alarm_option option;
enum calendar_alarm_mode mode;
};
/** \enum for tamper detection mode
*/
enum tamper_detection_mode { TAMPER_MODE_OFF = 0U, TAMPER_MODE_WAKE, TAMPER_MODE_CAPTURE, TAMPER_MODE_ACTL };
/** \enum for tamper detection mode
*/
enum tamper_id { TAMPID0 = 0U, TAMPID1, TAMPID2, TAMPID3, TAMPID4 };
/**
* \brief Initialize Calendar instance
*
* \param[in] dev The pointer to calendar device struct
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _calendar_init(struct calendar_dev *const dev);
/**
* \brief Deinitialize Calendar instance
*
* \param[in] dev The pointer to calendar device struct
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _calendar_deinit(struct calendar_dev *const dev);
/**
* \brief Enable Calendar instance
*
* \param[in] dev The pointer to calendar device struct
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _calendar_enable(struct calendar_dev *const dev);
/**
* \brief Disable Calendar instance
*
* \param[in] dev The pointer to calendar device struct
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _calendar_disable(struct calendar_dev *const dev);
/**
* \brief Set counter for calendar
*
* \param[in] dev The pointer to calendar device struct
* \param[in] counter The counter for set
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _calendar_set_counter(struct calendar_dev *const dev, const uint32_t counter);
/**
* \brief Get counter for calendar
*
* \param[in] dev The pointer to calendar device struct
*
* \return return current counter value
*/
uint32_t _calendar_get_counter(struct calendar_dev *const dev);
/**
* \brief Set compare value for calendar
*
* \param[in] dev The pointer to calendar device struct
* \param[in] comp The compare value for set
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _calendar_set_comp(struct calendar_dev *const dev, const uint32_t comp);
/**
* \brief Get compare value for calendar
*
* \param[in] dev The pointer to calendar device struct
*
* \return return current compare value
*/
uint32_t _calendar_get_comp(struct calendar_dev *const dev);
/**
* \brief Register callback for calendar alarm
*
* \param[in] dev The pointer to calendar device struct
* \param[in] callback The pointer to callback function
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _calendar_register_callback(struct calendar_dev *const dev, calendar_drv_cb_alarm_t callback);
/**
* \brief Set calendar IRQ
*
* \param[in] dev The pointer to calendar device struct
*/
void _calendar_set_irq(struct calendar_dev *const dev);
/**
* \brief Register callback for tamper detection
*
* \param[in] dev The pointer to calendar device struct
* \param[in] callback The pointer to callback function
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _tamper_register_callback(struct calendar_dev *const dev, tamper_drv_cb_t callback_tamper);
/**
* \brief Find tamper is detected on specified pin
*
* \param[in] dev The pointer to calendar device struct
* \param[in] enum Tamper ID number
*
* \return true on detection success and false on failure.
*/
bool _is_tamper_detected(struct calendar_dev *const dev, enum tamper_id tamper_id_pin);
/**
* \brief brief Clear the Tamper ID flag
*
* \param[in] dev The pointer to calendar device struct
* \param[in] enum Tamper ID number
*
* \return ERR_NONE
*/
int32_t _tamper_clear_tampid_flag(struct calendar_dev *const dev, enum tamper_id tamper_id_pin);
/**
* \brief Enable Debounce Asynchronous Feature
*
* \param[in] dev The pointer to calendar device struct
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _tamper_enable_debounce_asynchronous(struct calendar_dev *const dev);
/**
* \brief Disable Tamper Debounce Asynchronous Feature
*
* \param[in] dev The pointer to calendar device struct
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _tamper_disable_debounce_asynchronous(struct calendar_dev *const dev);
/**
* \brief Enable Tamper Debounce Majority Feature
*
* \param[in] dev The pointer to calendar device struct
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _tamper_enable_debounce_majority(struct calendar_dev *const dev);
/**
* \brief Enable Tamper Debounce Majority Feature
*
* \param[in] dev The pointer to calendar device struct
*
* \return ERR_NONE on success, or an error code on failure.
*/
int32_t _tamper_disable_debounce_majority(struct calendar_dev *const dev);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_RTC_H_INCLUDED */

56
Smol Watch Project/My Project/hal/include/hpl_core.h
View file

@ -1,56 +0,0 @@
/**
* \file
*
* \brief CPU core related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_CORE_H_INCLUDED
#define _HPL_CORE_H_INCLUDED
/**
* \addtogroup HPL Core
*
* \section hpl_core_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "hpl_core_port.h"
#ifdef __cplusplus
extern "C" {
#endif
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_CORE_H_INCLUDED */

97
Smol Watch Project/My Project/hal/include/hpl_delay.h
View file

@ -1,97 +0,0 @@
/**
* \file
*
* \brief Delay related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_DELAY_H_INCLUDED
#define _HPL_DELAY_H_INCLUDED
/**
* \addtogroup HPL Delay
*
* \section hpl_delay_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifndef _UNIT_TEST_
#include <compiler.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize delay functionality
*
* \param[in] hw The pointer to hardware instance
*/
void _delay_init(void *const hw);
/**
* \brief Retrieve the amount of cycles to delay for the given amount of us
*
* \param[in] us The amount of us to delay for
*
* \return The amount of cycles
*/
uint32_t _get_cycles_for_us(const uint16_t us);
/**
* \brief Retrieve the amount of cycles to delay for the given amount of ms
*
* \param[in] ms The amount of ms to delay for
*
* \return The amount of cycles
*/
uint32_t _get_cycles_for_ms(const uint16_t ms);
/**
* \brief Delay loop to delay n number of cycles
*
* \param[in] hw The pointer to hardware instance
* \param[in] cycles The amount of cycles to delay for
*/
void _delay_cycles(void *const hw, uint32_t cycles);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_DELAY_H_INCLUDED */

176
Smol Watch Project/My Project/hal/include/hpl_dma.h
View file

@ -1,176 +0,0 @@
/**
* \file
*
* \brief DMA related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_DMA_H_INCLUDED
#define _HPL_DMA_H_INCLUDED
/**
* \addtogroup HPL DMA
*
* \section hpl_dma_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#include <hpl_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
struct _dma_resource;
/**
* \brief DMA callback types
*/
enum _dma_callback_type { DMA_TRANSFER_COMPLETE_CB, DMA_TRANSFER_ERROR_CB };
/**
* \brief DMA interrupt callbacks
*/
struct _dma_callbacks {
void (*transfer_done)(struct _dma_resource *resource);
void (*error)(struct _dma_resource *resource);
};
/**
* \brief DMA resource structure
*/
struct _dma_resource {
struct _dma_callbacks dma_cb;
void * back;
};
/**
* \brief Initialize DMA
*
* This function does low level DMA configuration.
*
* \return initialize status
*/
int32_t _dma_init(void);
/**
* \brief Set destination address
*
* \param[in] channel DMA channel to set destination address for
* \param[in] dst Destination address
*
* \return setting status
*/
int32_t _dma_set_destination_address(const uint8_t channel, const void *const dst);
/**
* \brief Set source address
*
* \param[in] channel DMA channel to set source address for
* \param[in] src Source address
*
* \return setting status
*/
int32_t _dma_set_source_address(const uint8_t channel, const void *const src);
/**
* \brief Set next descriptor address
*
* \param[in] current_channel Current DMA channel to set next descriptor address
* \param[in] next_channel Next DMA channel used as next descriptor
*
* \return setting status
*/
int32_t _dma_set_next_descriptor(const uint8_t current_channel, const uint8_t next_channel);
/**
* \brief Enable/disable source address incrementation during DMA transaction
*
* \param[in] channel DMA channel to set source address for
* \param[in] enable True to enable, false to disable
*
* \return status of operation
*/
int32_t _dma_srcinc_enable(const uint8_t channel, const bool enable);
/**
* \brief Enable/disable Destination address incrementation during DMA transaction
*
* \param[in] channel DMA channel to set destination address for
* \param[in] enable True to enable, false to disable
*
* \return status of operation
*/
int32_t _dma_dstinc_enable(const uint8_t channel, const bool enable);
/**
* \brief Set the amount of data to be transfered per transaction
*
* \param[in] channel DMA channel to set data amount for
* \param[in] amount Data amount
*
* \return status of operation
*/
int32_t _dma_set_data_amount(const uint8_t channel, const uint32_t amount);
/**
* \brief Trigger DMA transaction on the given channel
*
* \param[in] channel DMA channel to trigger transaction on
*
* \return status of operation
*/
int32_t _dma_enable_transaction(const uint8_t channel, const bool software_trigger);
/**
* \brief Retrieves DMA resource structure
*
* \param[out] resource The resource to be retrieved
* \param[in] channel DMA channel to retrieve structure for
*
* \return status of operation
*/
int32_t _dma_get_channel_resource(struct _dma_resource **resource, const uint8_t channel);
/**
* \brief Enable/disable DMA interrupt
*
* \param[in] channel DMA channel to enable/disable interrupt for
* \param[in] type The type of interrupt to disable/enable if applicable
* \param[in] state Enable or disable
*/
void _dma_set_irq_state(const uint8_t channel, const enum _dma_callback_type type, const bool state);
#ifdef __cplusplus
}
#endif
#endif /* HPL_DMA_H_INCLUDED */

95
Smol Watch Project/My Project/hal/include/hpl_ext_irq.h
View file

@ -1,95 +0,0 @@
/**
* \file
*
* \brief External IRQ related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_EXT_IRQ_H_INCLUDED
#define _HPL_EXT_IRQ_H_INCLUDED
/**
* \addtogroup HPL EXT IRQ
*
* \section hpl_ext_irq_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize external interrupt module
*
* This function does low level external interrupt configuration.
*
* \param[in] cb The pointer to callback function from external interrupt
*
* \return Initialization status.
* \retval -1 External irq module is already initialized
* \retval 0 The initialization is completed successfully
*/
int32_t _ext_irq_init(void (*cb)(const uint32_t pin));
/**
* \brief Deinitialize external interrupt module
*
* \return Initialization status.
* \retval -1 External irq module is already deinitialized
* \retval 0 The de-initialization is completed successfully
*/
int32_t _ext_irq_deinit(void);
/**
* \brief Enable / disable external irq
*
* \param[in] pin Pin to enable external irq on
* \param[in] enable True to enable, false to disable
*
* \return Status of external irq enabling / disabling
* \retval -1 External irq module can't be enabled / disabled
* \retval 0 External irq module is enabled / disabled successfully
*/
int32_t _ext_irq_enable(const uint32_t pin, const bool enable);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_EXT_IRQ_H_INCLUDED */

185
Smol Watch Project/My Project/hal/include/hpl_gpio.h
View file

@ -1,185 +0,0 @@
/**
* \file
*
* \brief Port related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_GPIO_H_INCLUDED
#define _HPL_GPIO_H_INCLUDED
/**
* \addtogroup HPL Port
*
* \section hpl_port_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Macros for the pin and port group, lower 5
* bits stands for pin number in the group, higher 3
* bits stands for port group
*/
#define GPIO_PIN(n) (((n)&0x1Fu) << 0)
#define GPIO_PORT(n) ((n) >> 5)
#define GPIO(port, pin) ((((port)&0x7u) << 5) + ((pin)&0x1Fu))
#define GPIO_PIN_FUNCTION_OFF 0xffffffff
/**
* \brief PORT pull mode settings
*/
enum gpio_pull_mode { GPIO_PULL_OFF, GPIO_PULL_UP, GPIO_PULL_DOWN };
/**
* \brief PORT direction settins
*/
enum gpio_direction { GPIO_DIRECTION_OFF, GPIO_DIRECTION_IN, GPIO_DIRECTION_OUT };
/**
* \brief PORT group abstraction
*/
enum gpio_port { GPIO_PORTA, GPIO_PORTB, GPIO_PORTC, GPIO_PORTD, GPIO_PORTE };
/**
* \name HPL functions
*/
//@{
/**
* \brief Port initialization function
*
* Port initialization function should setup the port module based
* on a static configuration file, this function should normally
* not be called directly, but is a part of hal_init()
*/
void _gpio_init(void);
/**
* \brief Set direction on port with mask
*
* Set data direction for each pin, or disable the pin
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to the
* corresponding pin
* \param[in] direction GPIO_DIRECTION_OFF = set pin direction to input
* and disable input buffer to disable the pin
* GPIO_DIRECTION_IN = set pin direction to input
* and enable input buffer to enable the pin
* GPIO_DIRECTION_OUT = set pin direction to output
* and disable input buffer
*/
static inline void _gpio_set_direction(const enum gpio_port port, const uint32_t mask,
const enum gpio_direction direction);
/**
* \brief Set output level on port with mask
*
* Sets output state on pin to high or low with pin masking
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to
* the corresponding pin
* \param[in] level true = pin level is set to 1
* false = pin level is set to 0
*/
static inline void _gpio_set_level(const enum gpio_port port, const uint32_t mask, const bool level);
/**
* \brief Change output level to the opposite with mask
*
* Change pin output level to the opposite with pin masking
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] mask Bit mask where 1 means apply direction setting to
* the corresponding pin
*/
static inline void _gpio_toggle_level(const enum gpio_port port, const uint32_t mask);
/**
* \brief Get input levels on all port pins
*
* Get input level on all port pins, will read IN register if configured to
* input and OUT register if configured as output
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
*/
static inline uint32_t _gpio_get_level(const enum gpio_port port);
/**
* \brief Set pin pull mode
*
* Set pull mode on a single pin
*
* \notice This function will automatically change pin direction to input
*
* \param[in] port Ports are grouped into groups of maximum 32 pins,
* GPIO_PORTA = group 0, GPIO_PORTB = group 1, etc
* \param[in] pin The pin in the group that pull mode should be selected
* for
* \param[in] pull_mode GPIO_PULL_OFF = pull resistor on pin is disabled
* GPIO_PULL_DOWN = pull resistor on pin will pull pin
* level to ground level
* GPIO_PULL_UP = pull resistor on pin will pull pin
* level to VCC
*/
static inline void _gpio_set_pin_pull_mode(const enum gpio_port port, const uint8_t pin,
const enum gpio_pull_mode pull_mode);
/**
* \brief Set gpio function
*
* Select which function a gpio is used for
*
* \param[in] gpio The gpio to set function for
* \param[in] function The gpio function is given by a 32-bit wide bitfield
* found in the header files for the device
*
*/
static inline void _gpio_set_pin_function(const uint32_t gpio, const uint32_t function);
#include <hpl_gpio_base.h>
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_GPIO_H_INCLUDED */

205
Smol Watch Project/My Project/hal/include/hpl_i2c_m_async.h
View file

@ -1,205 +0,0 @@
/**
* \file
*
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_M_ASYNC_H_INCLUDED
#define _HPL_I2C_M_ASYNC_H_INCLUDED
#include "hpl_i2c_m_sync.h"
#include "hpl_irq.h"
#include "utils.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief i2c master callback names
*/
enum _i2c_m_async_callback_type {
I2C_M_ASYNC_DEVICE_ERROR,
I2C_M_ASYNC_DEVICE_TX_COMPLETE,
I2C_M_ASYNC_DEVICE_RX_COMPLETE
};
struct _i2c_m_async_device;
typedef void (*_i2c_complete_cb_t)(struct _i2c_m_async_device *i2c_dev);
typedef void (*_i2c_error_cb_t)(struct _i2c_m_async_device *i2c_dev, int32_t errcode);
/**
* \brief i2c callback pointers structure
*/
struct _i2c_m_async_callback {
_i2c_error_cb_t error;
_i2c_complete_cb_t tx_complete;
_i2c_complete_cb_t rx_complete;
};
/**
* \brief i2c device structure
*/
struct _i2c_m_async_device {
struct _i2c_m_service service;
void * hw;
struct _i2c_m_async_callback cb;
struct _irq_descriptor irq;
};
/**
* \name HPL functions
*/
/**
* \brief Initialize I2C in interrupt mode
*
* This function does low level I2C configuration.
*
* \param[in] i2c_dev The pointer to i2c interrupt device structure
* \param[in] hw The pointer to hardware instance
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_init(struct _i2c_m_async_device *const i2c_dev, void *const hw);
/**
* \brief Deinitialize I2C in interrupt mode
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_deinit(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_enable(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_disable(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Transfer data by I2C
*
* This function does low level I2C data transfer.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] msg The pointer to i2c msg structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_transfer(struct _i2c_m_async_device *const i2c_dev, struct _i2c_m_msg *msg);
/**
* \brief Set baud rate of I2C
*
* This function does low level I2C set baud rate.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] clkrate The clock rate(KHz) input to i2c module
* \param[in] baudrate The demand baud rate(KHz) of i2c module
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_set_baudrate(struct _i2c_m_async_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
/**
* \brief Register callback to I2C
*
* This function does low level I2C callback register.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] cb_type The callback type request
* \param[in] func The callback function pointer
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_async_register_callback(struct _i2c_m_async_device *i2c_dev, enum _i2c_m_async_callback_type cb_type,
FUNC_PTR func);
/**
* \brief Generate stop condition on the I2C bus
*
* This function will generate a stop condition on the I2C bus
*
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
*
* \return Operation status
* \retval 0 Operation executed successfully
* \retval <0 Operation failed
*/
int32_t _i2c_m_async_send_stop(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Returns the number of bytes left or not used in the I2C message buffer
*
* This function will return the number of bytes left (not written to the bus) or still free
* (not received from the bus) in the message buffer, depending on direction of transmission.
*
* \param[in] i2c_m_async_descriptor An i2c descriptor which is used to communicate through I2C
*
* \return Number of bytes or error code
* \retval >0 Positive number indicating bytes left
* \retval 0 Buffer is full/empty depending on direction
* \retval <0 Error code
*/
int32_t _i2c_m_async_get_bytes_left(struct _i2c_m_async_device *const i2c_dev);
/**
* \brief Enable/disable I2C master interrupt
*
* param[in] device The pointer to I2C master device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _i2c_m_async_set_irq_state(struct _i2c_m_async_device *const device, const enum _i2c_m_async_callback_type type,
const bool state);
#ifdef __cplusplus
}
#endif
#endif

185
Smol Watch Project/My Project/hal/include/hpl_i2c_m_sync.h
View file

@ -1,185 +0,0 @@
/**
* \file
*
* \brief I2C Master Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_M_SYNC_H_INCLUDED
#define _HPL_I2C_M_SYNC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief i2c flags
*/
#define I2C_M_RD 0x0001 /* read data, from slave to master */
#define I2C_M_BUSY 0x0100
#define I2C_M_TEN 0x0400 /* this is a ten bit chip address */
#define I2C_M_SEVEN 0x0800 /* this is a seven bit chip address */
#define I2C_M_FAIL 0x1000
#define I2C_M_STOP 0x8000 /* if I2C_FUNC_PROTOCOL_MANGLING */
/**
* \brief i2c Return codes
*/
#define I2C_OK 0 /* Operation successful */
#define I2C_ACK -1 /* Received ACK from device on I2C bus */
#define I2C_NACK -2 /* Received NACK from device on I2C bus */
#define I2C_ERR_ARBLOST -3 /* Arbitration lost */
#define I2C_ERR_BAD_ADDRESS -4 /* Bad address */
#define I2C_ERR_BUS -5 /* Bus error */
#define I2C_ERR_BUSY -6 /* Device busy */
#define I2c_ERR_PACKAGE_COLLISION -7 /* Package collision */
/**
* \brief i2c I2C Modes
*/
#define I2C_STANDARD_MODE 0x00
#define I2C_FASTMODE 0x01
#define I2C_HIGHSPEED_MODE 0x02
/**
* \brief i2c master message structure
*/
struct _i2c_m_msg {
uint16_t addr;
volatile uint16_t flags;
int32_t len;
uint8_t * buffer;
};
/**
* \brief i2c master service
*/
struct _i2c_m_service {
struct _i2c_m_msg msg;
uint16_t mode;
uint16_t trise;
};
/**
* \brief i2c sync master device structure
*/
struct _i2c_m_sync_device {
struct _i2c_m_service service;
void * hw;
};
/**
* \name HPL functions
*/
/**
* \brief Initialize I2C
*
* This function does low level I2C configuration.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] hw The pointer to hardware instance
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_init(struct _i2c_m_sync_device *const i2c_dev, void *const hw);
/**
* \brief Deinitialize I2C
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_deinit(struct _i2c_m_sync_device *const i2c_dev);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_enable(struct _i2c_m_sync_device *const i2c_dev);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] i2c_dev The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_disable(struct _i2c_m_sync_device *const i2c_dev);
/**
* \brief Transfer data by I2C
*
* This function does low level I2C data transfer.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] msg The pointer to i2c msg structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_transfer(struct _i2c_m_sync_device *const i2c_dev, struct _i2c_m_msg *msg);
/**
* \brief Set baud rate of I2C
*
* This function does low level I2C set baud rate.
*
* \param[in] i2c_dev The pointer to i2c device structure
* \param[in] clkrate The clock rate(KHz) input to i2c module
* \param[in] baudrate The demand baud rate(KHz) of i2c module
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_set_baudrate(struct _i2c_m_sync_device *const i2c_dev, uint32_t clkrate, uint32_t baudrate);
/**
* \brief Send send condition on the I2C bus
*
* This function will generate a stop condition on the I2C bus
*
* \param[in] i2c_dev The pointer to i2c device struct
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_m_sync_send_stop(struct _i2c_m_sync_device *const i2c_dev);
#ifdef __cplusplus
}
#endif
#endif

184
Smol Watch Project/My Project/hal/include/hpl_i2c_s_async.h
View file

@ -1,184 +0,0 @@
/**
* \file
*
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_S_ASYNC_H_INCLUDED
#define _HPL_I2C_S_ASYNC_H_INCLUDED
#include "hpl_i2c_s_sync.h"
#include "hpl_irq.h"
#include "utils.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief i2c callback types
*/
enum _i2c_s_async_callback_type { I2C_S_DEVICE_ERROR, I2C_S_DEVICE_TX, I2C_S_DEVICE_RX_COMPLETE };
/**
* \brief Forward declaration of I2C Slave device
*/
struct _i2c_s_async_device;
/**
* \brief i2c slave callback function type
*/
typedef void (*_i2c_s_async_cb_t)(struct _i2c_s_async_device *device);
/**
* \brief i2c slave callback pointers structure
*/
struct _i2c_s_async_callback {
void (*error)(struct _i2c_s_async_device *const device);
void (*tx)(struct _i2c_s_async_device *const device);
void (*rx_done)(struct _i2c_s_async_device *const device, const uint8_t data);
};
/**
* \brief i2c slave device structure
*/
struct _i2c_s_async_device {
void * hw;
struct _i2c_s_async_callback cb;
struct _irq_descriptor irq;
};
/**
* \name HPL functions
*/
/**
* \brief Initialize asynchronous I2C slave
*
* This function does low level I2C configuration.
*
* \param[in] device The pointer to i2c interrupt device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_init(struct _i2c_s_async_device *const device, void *const hw);
/**
* \brief Deinitialize asynchronous I2C in interrupt mode
*
* \param[in] device The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_deinit(struct _i2c_s_async_device *const device);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_enable(struct _i2c_s_async_device *const device);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_disable(struct _i2c_s_async_device *const device);
/**
* \brief Check if 10-bit addressing mode is on
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Cheking status
* \retval 1 10-bit addressing mode is on
* \retval 0 10-bit addressing mode is off
*/
int32_t _i2c_s_async_is_10bit_addressing_on(const struct _i2c_s_async_device *const device);
/**
* \brief Set I2C slave address
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] address Address to set
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_set_address(struct _i2c_s_async_device *const device, const uint16_t address);
/**
* \brief Write a byte to the given I2C instance
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] data Data to write
*/
void _i2c_s_async_write_byte(struct _i2c_s_async_device *const device, const uint8_t data);
/**
* \brief Retrieve I2C slave status
*
* \param[in] device The pointer to i2c slave device structure
*
*\return I2C slave status
*/
i2c_s_status_t _i2c_s_async_get_status(const struct _i2c_s_async_device *const device);
/**
* \brief Abort data transmission
*
* \param[in] device The pointer to i2c device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_async_abort_transmission(const struct _i2c_s_async_device *const device);
/**
* \brief Enable/disable I2C slave interrupt
*
* param[in] device The pointer to I2C slave device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] disable Enable or disable
*/
int32_t _i2c_s_async_set_irq_state(struct _i2c_s_async_device *const device, const enum _i2c_s_async_callback_type type,
const bool disable);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_I2C_S_ASYNC_H_INCLUDED */

184
Smol Watch Project/My Project/hal/include/hpl_i2c_s_sync.h
View file

@ -1,184 +0,0 @@
/**
* \file
*
* \brief I2C Slave Hardware Proxy Layer(HPL) declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_I2C_S_SYNC_H_INCLUDED
#define _HPL_I2C_S_SYNC_H_INCLUDED
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief I2C Slave status type
*/
typedef uint32_t i2c_s_status_t;
/**
* \brief i2c slave device structure
*/
struct _i2c_s_sync_device {
void *hw;
};
#include <compiler.h>
/**
* \name HPL functions
*/
/**
* \brief Initialize synchronous I2C slave
*
* This function does low level I2C configuration.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_init(struct _i2c_s_sync_device *const device, void *const hw);
/**
* \brief Deinitialize synchronous I2C slave
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_deinit(struct _i2c_s_sync_device *const device);
/**
* \brief Enable I2C module
*
* This function does low level I2C enable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_enable(struct _i2c_s_sync_device *const device);
/**
* \brief Disable I2C module
*
* This function does low level I2C disable.
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_disable(struct _i2c_s_sync_device *const device);
/**
* \brief Check if 10-bit addressing mode is on
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Cheking status
* \retval 1 10-bit addressing mode is on
* \retval 0 10-bit addressing mode is off
*/
int32_t _i2c_s_sync_is_10bit_addressing_on(const struct _i2c_s_sync_device *const device);
/**
* \brief Set I2C slave address
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] address Address to set
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_set_address(struct _i2c_s_sync_device *const device, const uint16_t address);
/**
* \brief Write a byte to the given I2C instance
*
* \param[in] device The pointer to i2c slave device structure
* \param[in] data Data to write
*/
void _i2c_s_sync_write_byte(struct _i2c_s_sync_device *const device, const uint8_t data);
/**
* \brief Retrieve I2C slave status
*
* \param[in] device The pointer to i2c slave device structure
*
*\return I2C slave status
*/
i2c_s_status_t _i2c_s_sync_get_status(const struct _i2c_s_sync_device *const device);
/**
* \brief Clear the Data Ready interrupt flag
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Return 0 for success and negative value for error
*/
int32_t _i2c_s_sync_clear_data_ready_flag(const struct _i2c_s_sync_device *const device);
/**
* \brief Read a byte from the given I2C instance
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Data received via I2C interface.
*/
uint8_t _i2c_s_sync_read_byte(const struct _i2c_s_sync_device *const device);
/**
* \brief Check if I2C is ready to send next byte
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Status of the ready check.
* \retval true if the I2C is ready to send next byte
* \retval false if the I2C is not ready to send next byte
*/
bool _i2c_s_sync_is_byte_sent(const struct _i2c_s_sync_device *const device);
/**
* \brief Check if there is data received by I2C
*
* \param[in] device The pointer to i2c slave device structure
*
* \return Status of the data received check.
* \retval true if the I2C has received a byte
* \retval false if the I2C has not received a byte
*/
bool _i2c_s_sync_is_byte_received(const struct _i2c_s_sync_device *const device);
#ifdef __cplusplus
}
#endif
#endif /* _HPL_I2C_S_SYNC_H_INCLUDED */

124
Smol Watch Project/My Project/hal/include/hpl_init.h
View file

@ -1,124 +0,0 @@
/**
* \file
*
* \brief Init related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_INIT_H_INCLUDED
#define _HPL_INIT_H_INCLUDED
/**
* \addtogroup HPL Init
*
* \section hpl_init_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name HPL functions
*/
//@{
/**
* \brief Initializes clock sources
*/
void _sysctrl_init_sources(void);
/**
* \brief Initializes Power Manager
*/
void _pm_init(void);
/**
* \brief Initialize generators
*/
void _gclk_init_generators(void);
/**
* \brief Initialize 32 kHz clock sources
*/
void _osc32kctrl_init_sources(void);
/**
* \brief Initialize clock sources
*/
void _oscctrl_init_sources(void);
/**
* \brief Initialize clock sources that need input reference clocks
*/
void _sysctrl_init_referenced_generators(void);
/**
* \brief Initialize clock sources that need input reference clocks
*/
void _oscctrl_init_referenced_generators(void);
/**
* \brief Initialize master clock generator
*/
void _mclk_init(void);
/**
* \brief Initialize clock generator
*/
void _lpmcu_misc_regs_init(void);
/**
* \brief Initialize clock generator
*/
void _pmc_init(void);
/**
* \brief Set performance level
*
* \param[in] level The performance level to set
*/
void _set_performance_level(const uint8_t level);
/**
* \brief Initialize the chip
*/
void _init_chip(void);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_INIT_H_INCLUDED */

116
Smol Watch Project/My Project/hal/include/hpl_irq.h
View file

@ -1,116 +0,0 @@
/**
* \file
*
* \brief IRQ related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_IRQ_H_INCLUDED
#define _HPL_IRQ_H_INCLUDED
/**
* \addtogroup HPL IRQ
*
* \section hpl_irq_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief IRQ descriptor
*/
struct _irq_descriptor {
void (*handler)(void *parameter);
void *parameter;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Retrieve current IRQ number
*
* \return The current IRQ number
*/
uint8_t _irq_get_current(void);
/**
* \brief Disable the given IRQ
*
* \param[in] n The number of IRQ to disable
*/
void _irq_disable(uint8_t n);
/**
* \brief Set the given IRQ
*
* \param[in] n The number of IRQ to set
*/
void _irq_set(uint8_t n);
/**
* \brief Clear the given IRQ
*
* \param[in] n The number of IRQ to clear
*/
void _irq_clear(uint8_t n);
/**
* \brief Enable the given IRQ
*
* \param[in] n The number of IRQ to enable
*/
void _irq_enable(uint8_t n);
/**
* \brief Register IRQ handler
*
* \param[in] number The number registered IRQ
* \param[in] irq The pointer to irq handler to register
*
* \return The status of IRQ handler registering
* \retval -1 Passed parameters were invalid
* \retval 0 The registering is completed successfully
*/
void _irq_register(const uint8_t number, struct _irq_descriptor *const irq);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_IRQ_H_INCLUDED */

37
Smol Watch Project/My Project/hal/include/hpl_missing_features.h
View file

@ -1,37 +0,0 @@
/**
* \file
*
* \brief Family-dependent missing features expected by HAL
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_MISSING_FEATURES
#define _HPL_MISSING_FEATURES
#endif /* _HPL_MISSING_FEATURES */

193
Smol Watch Project/My Project/hal/include/hpl_pwm.h
View file

@ -1,193 +0,0 @@
/**
* \file
*
* \brief PWM related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_PWM_H_INCLUDED
#define _HPL_PWM_H_INCLUDED
/**
* \addtogroup HPL PWM
*
* \section hpl_pwm_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief PWM callback types
*/
enum _pwm_callback_type { PWM_DEVICE_PERIOD_CB, PWM_DEVICE_ERROR_CB };
/**
* \brief PWM pulse-width period
*/
typedef uint32_t pwm_period_t;
/**
* \brief PWM device structure
*
* The PWM device structure forward declaration.
*/
struct _pwm_device;
/**
* \brief PWM interrupt callbacks
*/
struct _pwm_callback {
void (*pwm_period_cb)(struct _pwm_device *device);
void (*pwm_error_cb)(struct _pwm_device *device);
};
/**
* \brief PWM descriptor device structure
*/
struct _pwm_device {
struct _pwm_callback callback;
struct _irq_descriptor irq;
void * hw;
};
/**
* \brief PWM functions, pointers to low-level functions
*/
struct _pwm_hpl_interface {
int32_t (*init)(struct _pwm_device *const device, void *const hw);
void (*deinit)(struct _pwm_device *const device);
void (*start_pwm)(struct _pwm_device *const device);
void (*stop_pwm)(struct _pwm_device *const device);
void (*set_pwm_param)(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
bool (*is_pwm_enabled)(const struct _pwm_device *const device);
pwm_period_t (*pwm_get_period)(const struct _pwm_device *const device);
uint32_t (*pwm_get_duty)(const struct _pwm_device *const device);
void (*set_irq_state)(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
};
/**
* \brief Initialize TC
*
* This function does low level TC configuration.
*
* \param[in] device The pointer to PWM device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status.
*/
int32_t _pwm_init(struct _pwm_device *const device, void *const hw);
/**
* \brief Deinitialize TC
*
* \param[in] device The pointer to PWM device instance
*/
void _pwm_deinit(struct _pwm_device *const device);
/**
* \brief Retrieve offset of the given tc hardware instance
*
* \param[in] device The pointer to PWM device instance
*
* \return The offset of the given tc hardware instance
*/
uint8_t _pwm_get_hardware_offset(const struct _pwm_device *const device);
/**
* \brief Start hardware pwm
*
* \param[in] device The pointer to PWM device instance
*/
void _pwm_enable(struct _pwm_device *const device);
/**
* \brief Stop hardware pwm
*
* \param[in] device The pointer to PWM device instance
*/
void _pwm_disable(struct _pwm_device *const device);
/**
* \brief Set pwm parameter
*
* \param[in] device The pointer to PWM device instance
* \param[in] period Total period of one PWM cycle.
* \param[in] duty_cycle Period of PWM first half during one cycle.
*/
void _pwm_set_param(struct _pwm_device *const device, const pwm_period_t period, const pwm_period_t duty_cycle);
/**
* \brief Check if pwm is working
*
* \param[in] device The pointer to PWM device instance
*
* \return Check status.
* \retval true The given pwm is working
* \retval false The given pwm is not working
*/
bool _pwm_is_enabled(const struct _pwm_device *const device);
/**
* \brief Get pwm waveform period value
*
* \param[in] device The pointer to PWM device instance
*
* \return Period value.
*/
pwm_period_t _pwm_get_period(const struct _pwm_device *const device);
/**
* \brief Get pwm waveform duty cycle value
*
* \param[in] device The pointer to PWM device instance
*
* \return Duty cycle value
*/
uint32_t _pwm_get_duty(const struct _pwm_device *const device);
/**
* \brief Enable/disable PWM interrupt
*
* param[in] device The pointer to PWM device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] disable Enable or disable
*/
void _pwm_set_irq_state(struct _pwm_device *const device, const enum _pwm_callback_type type, const bool disable);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_PWM_H_INCLUDED */

92
Smol Watch Project/My Project/hal/include/hpl_reset.h
View file

@ -1,92 +0,0 @@
/**
* \file
*
* \brief Reset related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_RESET_H_INCLUDED
#define _HPL_RESET_H_INCLUDED
/**
* \addtogroup HPL Reset
*
* \section hpl_reset_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifndef _UNIT_TEST_
#include <compiler.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Reset reason enumeration
*
* The list of possible reset reasons.
*/
enum reset_reason {
RESET_REASON_POR = 1,
RESET_REASON_BOD12 = 2,
RESET_REASON_BOD33 = 4,
RESET_REASON_EXT = 16,
RESET_REASON_WDT = 32,
RESET_REASON_SYST = 64,
RESET_REASON_BACKUP = 128
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Retrieve the reset reason
*
* Retrieves the reset reason of the last MCU reset.
*
*\return An enum value indicating the reason of the last reset.
*/
enum reset_reason _get_reset_reason(void);
/**
* \brief Reset MCU
*/
void _reset_mcu(void);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_RESET_H_INCLUDED */

49
Smol Watch Project/My Project/hal/include/hpl_slcd.h
View file

@ -1,49 +0,0 @@
/**
* \file
*
* \brief SLCD common declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef HPL_SLCD_H_INCLUDED
#define HPL_SLCD_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#define SLCD_SEGID(com, seg) (((com) << 16) | (seg))
#define SLCD_COMNUM(segid) (((segid) >> 16) & 0xFF)
#define SLCD_SEGNUM(segid) ((segid)&0xFF)
#ifdef __cplusplus
}
#endif
#endif /* HPL_SLCD_H_INCLUDED */

154
Smol Watch Project/My Project/hal/include/hpl_slcd_sync.h
View file

@ -1,154 +0,0 @@
/**
* \file
*
* \brief SLCD Segment Liquid Crystal Display Controller(Sync) functionality
* declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef HPL_SLCD_SYNC_H_INCLUDED
#define HPL_SLCD_SYNC_H_INCLUDED
#include <hpl_slcd.h>
#include <utils_assert.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief SLCD sync device structure
*
* The SLCD device structure forward declaration.
*/
struct _slcd_sync_device;
struct _slcd_sync_device {
void *hw; /*!< Hardware module instance handler */
};
/**
* \brief Initialize SLCD Device Descriptor
*
* \param[in] desc SLCD descriptor to be initialized
* \param[in] hw The pointer to hardware instance
*/
int32_t _slcd_sync_init(struct _slcd_sync_device *const dev, void *const hw);
/**
* \brief Deinitialize SLCD Device Descriptor
*
* \param[in] desc SLCD device descriptor to be deinitialized
*/
int32_t _slcd_sync_deinit(struct _slcd_sync_device *const dev);
/**
* \brief Enable SLCD driver
*
* \param[in] dev SLCD device descriptor to be enabled
*/
int32_t _slcd_sync_enable(struct _slcd_sync_device *const dev);
/**
* \brief Disable SLCD driver
*
* \param[in] dev SLCD Device descriptor to be disabled
*/
int32_t _slcd_sync_disable(struct _slcd_sync_device *const dev);
/**
* \brief Turn on a Segment
*
* \param[in] dev SLCD Device descriptor
* \param[in] seg Segment id
* value is (common terminals << 16 | segment terminal)
*/
int32_t _slcd_sync_seg_on(struct _slcd_sync_device *const dev, uint32_t seg);
/**
* \brief Turn off a Segment
*
* \param[in] dev SLCD Device descriptor
* \param[in] seg Segment id
* value is (common terminals << 16 | segment terminal)
*/
int32_t _slcd_sync_seg_off(struct _slcd_sync_device *const dev, uint32_t seg);
/**
* \brief Blink a Segment
*
* \param[in] dev SLCD Device descriptor
* \param[in] seg Segment index
* value is (common terminals << 16 | segment terminal)
* \param[in] period Blink period, unit is million second
*/
int32_t _slcd_sync_seg_blink(struct _slcd_sync_device *const dev, uint32_t seg, const uint32_t period);
/**
* \brief Displays a character
*
* \param[in] dev SLCD Device descriptor
* \param[in] character Character to be displayed
* \param[in] index Index of Character Mapping Group
*/
int32_t _slcd_sync_write_char(struct _slcd_sync_device *const dev, const uint8_t character, uint32_t index);
/**
* \brief Start animation play by a segment array
*
* \param[in] dev SLCD Device descriptor
* \param[in] segs Segment array
* \param[in] len Length of the segment array
* \param[in] period Period(milliseconds) of the each segment to animation
*/
int32_t _slcd_sync_start_animation(struct _slcd_sync_device *const dev, const uint32_t segs[], uint32_t len,
const uint32_t period);
/**
* \brief Stop animation play by a segment array
*
* \param[in] dev SLCD device descriptor
* \param[in] segs Segment array
* \param[in] len Length of the segment array
*/
int32_t _slcd_sync_stop_animation(struct _slcd_sync_device *const dev, const uint32_t segs[], uint32_t len);
/**
* \brief Set animation Frequency
*
* \param[in] dev SLCD Device descriptor
* \param[in] period Period(million second) of the each segment to animation
*/
int32_t _slcd_sync_set_animation_period(struct _slcd_sync_device *const dev, const uint32_t period);
#ifdef __cplusplus
}
#endif
#endif

88
Smol Watch Project/My Project/hal/include/hpl_sleep.h
View file

@ -1,88 +0,0 @@
/**
* \file
*
* \brief Sleep related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SLEEP_H_INCLUDED
#define _HPL_SLEEP_H_INCLUDED
/**
* \addtogroup HPL Sleep
*
* \section hpl_sleep_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifndef _UNIT_TEST_
#include <compiler.h>
#endif
#ifdef __cplusplus
extern "C" {
#endif
/**
* \name HPL functions
*/
//@{
/**
* \brief Set the sleep mode for the device
*
* This function sets the sleep mode for the device.
* For an overview of which systems are disabled in sleep for the different
* sleep modes see datasheet.
*
* \param[in] mode Sleep mode to use
*
* \return the status of a sleep request
* \retval -1 The requested sleep mode was invalid
* \retval 0 The operation completed successfully, sleep mode is set
*/
int32_t _set_sleep_mode(const uint8_t mode);
/**
* \brief Reset MCU
*/
void _reset_mcu(void);
/**
* \brief Put MCU to sleep
*/
void _go_to_sleep(void);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_SLEEP_H_INCLUDED */

163
Smol Watch Project/My Project/hal/include/hpl_spi.h
View file

@ -1,163 +0,0 @@
/**
* \file
*
* \brief SPI related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_H_INCLUDED
#define _HPL_SPI_H_INCLUDED
#include <compiler.h>
#include <utils.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief SPI Dummy char is used when reading data from the SPI slave
*/
#define SPI_DUMMY_CHAR 0x1ff
/**
* \brief SPI message to let driver to process
*/
//@{
struct spi_msg {
/** Pointer to the output data buffer */
uint8_t *txbuf;
/** Pointer to the input data buffer */
uint8_t *rxbuf;
/** Size of the message data in SPI characters */
uint32_t size;
};
//@}
/**
* \brief SPI transfer modes
* SPI transfer mode controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
*/
enum spi_transfer_mode {
/** Leading edge is rising edge, data sample on leading edge. */
SPI_MODE_0,
/** Leading edge is rising edge, data sample on trailing edge. */
SPI_MODE_1,
/** Leading edge is falling edge, data sample on leading edge. */
SPI_MODE_2,
/** Leading edge is falling edge, data sample on trailing edge. */
SPI_MODE_3
};
/**
* \brief SPI character sizes
* The character size influence the way the data is sent/received.
* For char size <= 8 data is stored byte by byte.
* For char size between 9 ~ 16 data is stored in 2-byte length.
* Note that the default and recommended char size is 8 bit since it's
* supported by all system.
*/
enum spi_char_size {
/** Character size is 8 bit. */
SPI_CHAR_SIZE_8 = 0,
/** Character size is 9 bit. */
SPI_CHAR_SIZE_9 = 1,
/** Character size is 10 bit. */
SPI_CHAR_SIZE_10 = 2,
/** Character size is 11 bit. */
SPI_CHAR_SIZE_11 = 3,
/** Character size is 12 bit. */
SPI_CHAR_SIZE_12 = 4,
/** Character size is 13 bit. */
SPI_CHAR_SIZE_13 = 5,
/** Character size is 14 bit. */
SPI_CHAR_SIZE_14 = 6,
/** Character size is 15 bit. */
SPI_CHAR_SIZE_15 = 7,
/** Character size is 16 bit. */
SPI_CHAR_SIZE_16 = 8
};
/**
* \brief SPI data order
*/
enum spi_data_order {
/** MSB goes first. */
SPI_DATA_ORDER_MSB_1ST = 0,
/** LSB goes first. */
SPI_DATA_ORDER_LSB_1ST = 1
};
/** \brief Transfer descriptor for SPI
* Transfer descriptor holds TX and RX buffers
*/
struct spi_xfer {
/** Pointer to data buffer to TX */
uint8_t *txbuf;
/** Pointer to data buffer to RX */
uint8_t *rxbuf;
/** Size of data characters to TX & RX */
uint32_t size;
};
/** SPI generic driver. */
struct spi_dev {
/** Pointer to the hardware base or private data for special device. */
void *prvt;
/** Reference start of sync/async variables */
uint32_t sync_async_misc[1];
};
/**
* \brief Calculate the baudrate value for hardware to use to set baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] clk Clock frequency (Hz) for baudrate generation.
* \param[in] baud Target baudrate (bps).
* \return Error or baudrate value.
* \retval >0 Baudrate value.
* \retval ERR_INVALID_ARG Calculation fail.
*/
int32_t _spi_calc_baud_val(struct spi_dev *dev, const uint32_t clk, const uint32_t baud);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_H_INCLUDED */

131
Smol Watch Project/My Project/hal/include/hpl_spi_async.h
View file

@ -1,131 +0,0 @@
/**
* \file
*
* \brief Common SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_ASYNC_H_INCLUDED
#define _HPL_SPI_ASYNC_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_irq.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Callbacks the SPI driver must offer in async mode
*/
//@{
/** The callback types */
enum _spi_async_dev_cb_type {
/** Callback type for transmit, see \ref _spi_async_dev_cb_xfer_t. */
SPI_DEV_CB_TX,
/** Callback type for receive, see \ref _spi_async_dev_cb_xfer_t. */
SPI_DEV_CB_RX,
/** Callback type for \ref _spi_async_dev_cb_complete_t. */
SPI_DEV_CB_COMPLETE,
/** Callback type for error */
SPI_DEV_CB_ERROR,
/** Number of callbacks. */
SPI_DEV_CB_N
};
struct _spi_async_dev;
/** \brief The prototype for callback on SPI transfer error.
* If status code is zero, it indicates the normal completion, that is,
* SS deactivation.
* If status code belows zero, it indicates complete.
*/
typedef void (*_spi_async_dev_cb_error_t)(struct _spi_async_dev *dev, int32_t status);
/** \brief The prototype for callback on SPI transmit/receive event
* For TX, the callback is invoked when transmit is done or ready to start
* transmit.
* For RX, the callback is invoked when receive is done or ready to read data,
* see \ref _spi_async_dev_read_one_t on data reading.
* Without DMA enabled, the callback is invoked on each character event.
* With DMA enabled, the callback is invoked on DMA buffer done.
*/
typedef void (*_spi_async_dev_cb_xfer_t)(struct _spi_async_dev *dev);
/**
* \brief The callbacks offered by SPI driver
*/
struct _spi_async_dev_callbacks {
/** TX callback, see \ref _spi_async_dev_cb_xfer_t. */
_spi_async_dev_cb_xfer_t tx;
/** RX callback, see \ref _spi_async_dev_cb_xfer_t. */
_spi_async_dev_cb_xfer_t rx;
/** Complete or complete callback, see \ref _spi_async_dev_cb_complete_t. */
_spi_async_dev_cb_xfer_t complete;
/** Error callback, see \ref */
_spi_async_dev_cb_error_t err;
};
//@}
/**
* \brief SPI async driver
*/
//@{
/** SPI driver to support async HAL */
struct _spi_async_dev {
/** Pointer to the hardware base or private data for special device. */
void *prvt;
/** Data size, number of bytes for each character */
uint8_t char_size;
/** Dummy byte used in master mode when reading the slave */
uint16_t dummy_byte;
/** \brief Pointer to callback functions, ignored for polling mode
* Pointer to the callback functions so that initialize the driver to
* handle interrupts.
*/
struct _spi_async_dev_callbacks callbacks;
/** IRQ instance for SPI device. */
struct _irq_descriptor irq;
};
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_ASYNC_H_INCLUDED */

243
Smol Watch Project/My Project/hal/include/hpl_spi_m_async.h
View file

@ -1,243 +0,0 @@
/**
* \file
*
* \brief SPI Slave Async related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_M_ASYNC_H_INCLUDED
#define _HPL_SPI_M_ASYNC_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_spi_async.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI async device driver. */
#define _spi_m_async_dev _spi_async_dev
#define _spi_m_async_dev_cb_type _spi_async_dev_cb_type
/** Uses common SPI async device driver complete callback type. */
#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t
/** Uses common SPI async device driver transfer callback type. */
#define _spi_m_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access with interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_init(struct _spi_m_async_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_deinit(struct _spi_m_async_dev *dev);
/**
* \brief Enable SPI for access with interrupts
* Enable the SPI and enable callback generation of receive and error
* interrupts.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_enable(struct _spi_m_async_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI and interrupts. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_disable(struct _spi_m_async_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_mode(struct _spi_m_async_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
* how it's generated.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_baudrate(struct _spi_m_async_dev *dev, const uint32_t baud_val);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_char_size(struct _spi_m_async_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_async_set_data_order(struct _spi_m_async_dev *dev, const enum spi_data_order dord);
/**
* \brief Enable interrupt on character output
*
* Enable interrupt when a new character can be written
* to the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable output interrupt
* false = disable output interrupt
*
* \return Status code
* \retval 0 Ok status
*/
int32_t _spi_m_async_enable_tx(struct _spi_m_async_dev *dev, bool state);
/**
* \brief Enable interrupt on character input
*
* Enable interrupt when a new character is ready to be
* read from the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_m_async_enable_rx(struct _spi_m_async_dev *dev, bool state);
/**
* \brief Enable interrupt on after data transmission complate
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_m_async_enable_tx_complete(struct _spi_m_async_dev *dev, bool state);
/**
* \brief Read one character to SPI device instance
* \param[in, out] dev Pointer to the SPI device instance.
*
* \return Character read from SPI module
*/
uint16_t _spi_m_async_read_one(struct _spi_m_async_dev *dev);
/**
* \brief Write one character to assigned buffer
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] data
*
* \return Status code of write operation
* \retval 0 Write operation OK
*/
int32_t _spi_m_async_write_one(struct _spi_m_async_dev *dev, uint16_t data);
/**
* \brief Register the SPI device callback
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] cb_type The callback type.
* \param[in] func The callback function to register. NULL to disable callback.
* \return Always 0.
*/
int32_t _spi_m_async_register_callback(struct _spi_m_async_dev *dev, const enum _spi_m_async_dev_cb_type cb_type,
const FUNC_PTR func);
/**
* \brief Enable/disable SPI master interrupt
*
* param[in] device The pointer to SPI master device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _spi_m_async_set_irq_state(struct _spi_m_async_dev *const device, const enum _spi_m_async_dev_cb_type type,
const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_M_ASYNC_H_INCLUDED */

182
Smol Watch Project/My Project/hal/include/hpl_spi_m_dma.h
View file

@ -1,182 +0,0 @@
/**
* \file
*
* \brief SPI Master DMA related functionality declaration.
*
* Copyright (c) 2016-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_M_DMA_H_INCLUDED
#define _HPL_SPI_M_DMA_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_spi_dma.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI dma device driver. */
#define _spi_m_dma_dev _spi_dma_dev
#define _spi_m_dma_dev_cb_type _spi_dma_dev_cb_type
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access with interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_init(struct _spi_m_dma_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_deinit(struct _spi_m_dma_dev *dev);
/**
* \brief Enable SPI for access with interrupts
* Enable the SPI and enable callback generation of receive and error
* interrupts.
* \param[in] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_enable(struct _spi_m_dma_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI and interrupts. Deactivate all CS pins if works as master.
* \param[in] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_disable(struct _spi_m_dma_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 ERR_NONE is operation done successfully.
*/
int32_t _spi_m_dma_set_mode(struct _spi_m_dma_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in] dev Pointer to the SPI device instance.
* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
* how it's generated.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_dma_set_baudrate(struct _spi_m_dma_dev *dev, const uint32_t baud_val);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_dma_set_char_size(struct _spi_m_dma_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_dma_set_data_order(struct _spi_m_dma_dev *dev, const enum spi_data_order dord);
/**
* \brief Register the SPI device callback
* \param[in] dev Pointer to the SPI device instance.
* \param[in] cb_type The callback type.
* \param[in] func The callback function to register. NULL to disable callback.
* \return Always 0.
*/
void _spi_m_dma_register_callback(struct _spi_m_dma_dev *dev, enum _spi_dma_dev_cb_type, _spi_dma_cb_t func);
/** \brief Do SPI data transfer (TX & RX) with DMA
* Log the TX & RX buffers and transfer them in background. It never blocks.
*
* \param[in] dev Pointer to the SPI device instance.
* \param[in] txbuf Pointer to the transfer information (\ref spi_transfer).
* \param[out] rxbuf Pointer to the receiver information (\ref spi_receive).
* \param[in] length spi transfer data length.
*
* \return Operation status.
* \retval ERR_NONE Success.
* \retval ERR_BUSY Busy.
*/
int32_t _spi_m_dma_transfer(struct _spi_m_dma_dev *dev, uint8_t const *txbuf, uint8_t *const rxbuf,
const uint16_t length);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_M_DMA_H_INCLUDED */

166
Smol Watch Project/My Project/hal/include/hpl_spi_m_sync.h
View file

@ -1,166 +0,0 @@
/**
* \file
*
* \brief SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_M_SYNC_H_INCLUDED
#define _HPL_SPI_M_SYNC_H_INCLUDED
#include <hpl_spi.h>
#include <hpl_spi_sync.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI sync device driver. */
#define _spi_m_sync_dev _spi_sync_dev
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access without interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_init(struct _spi_m_sync_dev *dev, void *const hw);
/**
* \brief Deinitialize SPI
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_deinit(struct _spi_m_sync_dev *dev);
/**
* \brief Enable SPI for access without interrupts
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_enable(struct _spi_m_sync_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_disable(struct _spi_m_sync_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_mode(struct _spi_m_sync_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] baud_val The SPI baudrate value, see \ref _spi_calc_baud_val() on
* how it's generated.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_baudrate(struct _spi_m_sync_dev *dev, const uint32_t baud_val);
/**
* \brief Set SPI char size
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_char_size(struct _spi_m_sync_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_m_sync_set_data_order(struct _spi_m_sync_dev *dev, const enum spi_data_order dord);
/**
* \brief Transfer the whole message without interrupt
* Transfer the message, it will keep waiting until the message finish or
* error.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] msg Pointer to the message instance to process.
* \return Error or number of characters transferred.
* \retval ERR_BUSY SPI hardware is not ready to start transfer (not
* enabled, busy applying settings, ...).
* \retval SPI_ERR_OVERFLOW Overflow error.
* \retval >=0 Number of characters transferred.
*/
int32_t _spi_m_sync_trans(struct _spi_m_sync_dev *dev, const struct spi_msg *msg);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_M_SYNC_H_INCLUDED */

232
Smol Watch Project/My Project/hal/include/hpl_spi_s_async.h
View file

@ -1,232 +0,0 @@
/**
* \file
*
* \brief SPI Slave Async related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_S_ASYNC_H_INCLUDED
#define _HPL_SPI_S_ASYNC_H_INCLUDED
#include <hpl_spi_async.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI async device driver. */
#define _spi_s_async_dev _spi_async_dev
#define _spi_s_async_dev_cb_type _spi_async_dev_cb_type
/** Uses common SPI async device driver complete callback type. */
#define _spi_m_async_dev_cb_error_t _spi_async_dev_cb_error_t
/** Uses common SPI async device driver transfer callback type. */
#define _spi_s_async_dev_cb_xfer_t _spi_async_dev_cb_xfer_t
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access with interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_init(struct _spi_s_async_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_deinit(struct _spi_s_async_dev *dev);
/**
* \brief Enable SPI for access with interrupts
* Enable the SPI and enable callback generation of receive and error
* interrupts.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_enable(struct _spi_s_async_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI and interrupts. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_disable(struct _spi_s_async_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_set_mode(struct _spi_s_async_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_set_char_size(struct _spi_s_async_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_async_set_data_order(struct _spi_s_async_dev *dev, const enum spi_data_order dord);
/**
* \brief Enable interrupt on character output
*
* Enable interrupt when a new character can be written
* to the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable output interrupt
* false = disable output interrupt
*
* \return Status code
* \retval 0 Ok status
*/
int32_t _spi_s_async_enable_tx(struct _spi_s_async_dev *dev, bool state);
/**
* \brief Enable interrupt on character input
*
* Enable interrupt when a new character is ready to be
* read from the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_s_async_enable_rx(struct _spi_s_async_dev *dev, bool state);
/**
* \brief Enable interrupt on Slave Select (SS) rising
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retvat 0 OK Status
*/
int32_t _spi_s_async_enable_ss_detect(struct _spi_s_async_dev *dev, bool state);
/**
* \brief Read one character to SPI device instance
* \param[in, out] dev Pointer to the SPI device instance.
*
* \return Character read from SPI module
*/
uint16_t _spi_s_async_read_one(struct _spi_s_async_dev *dev);
/**
* \brief Write one character to assigned buffer
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] data
*
* \return Status code of write operation
* \retval 0 Write operation OK
*/
int32_t _spi_s_async_write_one(struct _spi_s_async_dev *dev, uint16_t data);
/**
* \brief Register the SPI device callback
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] cb_type The callback type.
* \param[in] func The callback function to register. NULL to disable callback.
* \return Always 0.
*/
int32_t _spi_s_async_register_callback(struct _spi_s_async_dev *dev, const enum _spi_s_async_dev_cb_type cb_type,
const FUNC_PTR func);
/**
* \brief Enable/disable SPI slave interrupt
*
* param[in] device The pointer to SPI slave device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _spi_s_async_set_irq_state(struct _spi_s_async_dev *const device, const enum _spi_async_dev_cb_type type,
const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_S_ASYNC_H_INCLUDED */

232
Smol Watch Project/My Project/hal/include/hpl_spi_s_sync.h
View file

@ -1,232 +0,0 @@
/**
* \file
*
* \brief SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_S_SYNC_H_INCLUDED
#define _HPL_SPI_S_SYNC_H_INCLUDED
#include <hpl_spi_sync.h>
/**
* \addtogroup hpl_spi HPL SPI
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** Uses common SPI sync device driver. */
#define _spi_s_sync_dev _spi_sync_dev
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize SPI for access without interrupts
* It will load default hardware configuration and software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] hw Pointer to the hardware base.
* \return Operation status.
* \retval ERR_INVALID_ARG Input parameter problem.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval ERR_DENIED SPI has been enabled.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_init(struct _spi_s_sync_dev *dev, void *const hw);
/**
* \brief Initialize SPI for access with interrupts
* Disable, reset the hardware and the software struct.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_deinit(struct _spi_s_sync_dev *dev);
/**
* \brief Enable SPI for access without interrupts
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval ERR_BUSY SPI hardware not ready (resetting).
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_enable(struct _spi_s_sync_dev *dev);
/**
* \brief Disable SPI for access without interrupts
* Disable SPI. Deactivate all CS pins if works as master.
* \param[in, out] dev Pointer to the SPI device instance.
* \return Operation status.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_disable(struct _spi_s_sync_dev *dev);
/**
* \brief Set SPI transfer mode
* Set SPI transfer mode (\ref spi_transfer_mode),
* which controls clock polarity and clock phase.
* Mode 0: leading edge is rising edge, data sample on leading edge.
* Mode 1: leading edge is rising edge, data sample on trailing edge.
* Mode 2: leading edge is falling edge, data sample on leading edge.
* Mode 3: leading edge is falling edge, data sample on trailing edge.
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] mode The SPI transfer mode.
* \return Operation status.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_set_mode(struct _spi_s_sync_dev *dev, const enum spi_transfer_mode mode);
/**
* \brief Set SPI baudrate
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] char_size The character size, see \ref spi_char_size.
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_set_char_size(struct _spi_s_sync_dev *dev, const enum spi_char_size char_size);
/**
* \brief Set SPI data order
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] dord SPI data order (LSB/MSB first).
* \return Operation status.
* \retval ERR_INVALID_ARG The character size is not supported.
* \retval ERR_BUSY SPI is not ready to accept new setting.
* \retval 0 Operation done successfully.
*/
int32_t _spi_s_sync_set_data_order(struct _spi_s_sync_dev *dev, const enum spi_data_order dord);
/**
* \brief Enable interrupt on character output
*
* Enable interrupt when a new character can be written
* to the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable output interrupt
* false = disable output interrupt
*
* \return Status code
* \retval 0 Ok status
*/
int32_t _spi_s_sync_enable_tx(struct _spi_s_sync_dev *dev, bool state);
/**
* \brief Enable interrupt on character input
*
* Enable interrupt when a new character is ready to be
* read from the SPI device.
*
* \param[in] dev Pointer to the SPI device instance
* \param[in] state true = enable input interrupts
* false = disable input interrupt
*
* \return Status code
* \retval 0 OK Status
*/
int32_t _spi_s_sync_enable_rx(struct _spi_s_sync_dev *dev, bool state);
/**
* \brief Read one character to SPI device instance
* \param[in, out] dev Pointer to the SPI device instance.
*
* \return Character read from SPI module
*/
uint16_t _spi_s_sync_read_one(struct _spi_s_sync_dev *dev);
/**
* \brief Write one character to assigned buffer
* \param[in, out] dev Pointer to the SPI device instance.
* \param[in] data
*
* \return Status code of write operation
* \retval 0 Write operation OK
*/
int32_t _spi_s_sync_write_one(struct _spi_s_sync_dev *dev, uint16_t data);
/**
* \brief Check if TX ready
*
* \param[in] dev Pointer to the SPI device instance
*
* \return TX ready state
* \retval true TX ready
* \retval false TX not ready
*/
bool _spi_s_sync_is_tx_ready(struct _spi_s_sync_dev *dev);
/**
* \brief Check if RX character ready
*
* \param[in] dev Pointer to the SPI device instance
*
* \return RX character ready state
* \retval true RX character ready
* \retval false RX character not ready
*/
bool _spi_s_sync_is_rx_ready(struct _spi_s_sync_dev *dev);
/**
* \brief Check if SS deactiviation detected
*
* \param[in] dev Pointer to the SPI device instance
*
* \return SS deactiviation state
* \retval true SS deactiviation detected
* \retval false SS deactiviation not detected
*/
bool _spi_s_sync_is_ss_deactivated(struct _spi_s_sync_dev *dev);
/**
* \brief Check if error is detected
*
* \param[in] dev Pointer to the SPI device instance
*
* \return Error detection state
* \retval true Error detected
* \retval false Error not detected
*/
bool _spi_s_sync_is_error(struct _spi_s_sync_dev *dev);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_S_SYNC_H_INCLUDED */

70
Smol Watch Project/My Project/hal/include/hpl_spi_sync.h
View file

@ -1,70 +0,0 @@
/**
* \file
*
* \brief Common SPI related functionality declaration.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SPI_SYNC_H_INCLUDED
#define _HPL_SPI_SYNC_H_INCLUDED
#include <compiler.h>
#include <utils.h>
#include <hpl_spi.h>
/**
* \addtogroup hpl_spi HPL SPI
*
* \section hpl_spi_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#ifdef __cplusplus
extern "C" {
#endif
/** SPI driver to support sync HAL */
struct _spi_sync_dev {
/** Pointer to the hardware base or private data for special device. */
void *prvt;
/** Data size, number of bytes for each character */
uint8_t char_size;
/** Dummy byte used in master mode when reading the slave */
uint16_t dummy_byte;
};
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* ifndef _HPL_SPI_SYNC_H_INCLUDED */

94
Smol Watch Project/My Project/hal/include/hpl_time_measure.h
View file

@ -1,94 +0,0 @@
/**
* \file
*
* \brief Time measure related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_TIME_MEASURE_H_INCLUDED
#define _HPL_TIME_MEASURE_H_INCLUDED
/**
* \addtogroup HPL Time measure
*
* \section hpl_time_measure_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief System time type
*/
typedef uint32_t system_time_t;
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize system time module
*
* \param[in] hw The pointer to hardware instance to initialize
*/
void _system_time_init(void *const hw);
/**
* \brief Deinitialize system time module
*
* \param[in] hw The pointer to hardware instance to initialize
*/
void _system_time_deinit(void *const hw);
/**
* \brief Get system time
*
* \param[in] hw The pointer to hardware instance to initialize
*/
system_time_t _system_time_get(const void *const hw);
/**
* \brief Get maximum possible system time
*
* \param[in] hw The pointer to hardware instance to initialize
*/
system_time_t _system_time_get_max_time_value(const void *const hw);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_TIME_MEASURE_H_INCLUDED */

160
Smol Watch Project/My Project/hal/include/hpl_timer.h
View file

@ -1,160 +0,0 @@
/**
* \file
*
* \brief Timer related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_TIMER_H_INCLUDED
#define _HPL_TIMER_H_INCLUDED
/**
* \addtogroup HPL Timer
*
* \section hpl_timer_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#include <hpl_irq.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief Timer device structure
*
* The Timer device structure forward declaration.
*/
struct _timer_device;
/**
* \brief Timer interrupt callbacks
*/
struct _timer_callbacks {
void (*period_expired)(struct _timer_device *device);
};
/**
* \brief Timer device structure
*/
struct _timer_device {
struct _timer_callbacks timer_cb;
struct _irq_descriptor irq;
void * hw;
};
/**
* \brief Timer functions, pointers to low-level functions
*/
struct _timer_hpl_interface {
int32_t (*init)(struct _timer_device *const device, void *const hw);
void (*deinit)(struct _timer_device *const device);
void (*start_timer)(struct _timer_device *const device);
void (*stop_timer)(struct _timer_device *const device);
void (*set_timer_period)(struct _timer_device *const device, const uint32_t clock_cycles);
uint32_t (*get_period)(const struct _timer_device *const device);
bool (*is_timer_started)(const struct _timer_device *const device);
void (*set_timer_irq)(struct _timer_device *const device);
};
/**
* \brief Initialize TCC
*
* This function does low level TCC configuration.
*
* \param[in] device The pointer to timer device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status.
*/
int32_t _timer_init(struct _timer_device *const device, void *const hw);
/**
* \brief Deinitialize TCC
*
* \param[in] device The pointer to timer device instance
*/
void _timer_deinit(struct _timer_device *const device);
/**
* \brief Start hardware timer
*
* \param[in] device The pointer to timer device instance
*/
void _timer_start(struct _timer_device *const device);
/**
* \brief Stop hardware timer
*
* \param[in] device The pointer to timer device instance
*/
void _timer_stop(struct _timer_device *const device);
/**
* \brief Set timer period
*
* \param[in] device The pointer to timer device instance
*/
void _timer_set_period(struct _timer_device *const device, const uint32_t clock_cycles);
/**
* \brief Retrieve timer period
*
* \param[in] device The pointer to timer device instance
*
* \return Timer period
*/
uint32_t _timer_get_period(const struct _timer_device *const device);
/**
* \brief Check if timer is running
*
* \param[in] device The pointer to timer device instance
*
* \return Check status.
* \retval true The given timer is running
* \retval false The given timer is not running
*/
bool _timer_is_started(const struct _timer_device *const device);
/**
* \brief Set timer IRQ
*
* \param[in] device The pointer to timer device instance
*/
void _timer_set_irq(struct _timer_device *const device);
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_TIMER_H_INCLUDED */

113
Smol Watch Project/My Project/hal/include/hpl_usart.h
View file

@ -1,113 +0,0 @@
/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_USART_H_INCLUDED
#define _HPL_USART_H_INCLUDED
/**
* \addtogroup HPL USART SYNC
*
* \section hpl_usart_sync_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief USART flow control state
*/
union usart_flow_control_state {
struct {
uint8_t cts : 1;
uint8_t rts : 1;
uint8_t unavailable : 1;
uint8_t reserved : 5;
} bit;
uint8_t value;
};
/**
* \brief USART baud rate mode
*/
enum usart_baud_rate_mode { USART_BAUDRATE_ASYNCH_ARITHMETIC, USART_BAUDRATE_ASYNCH_FRACTIONAL, USART_BAUDRATE_SYNCH };
/**
* \brief USART data order
*/
enum usart_data_order { USART_DATA_ORDER_MSB = 0, USART_DATA_ORDER_LSB = 1 };
/**
* \brief USART mode
*/
enum usart_mode { USART_MODE_ASYNCHRONOUS = 0, USART_MODE_SYNCHRONOUS = 1 };
/**
* \brief USART parity
*/
enum usart_parity {
USART_PARITY_EVEN = 0,
USART_PARITY_ODD = 1,
USART_PARITY_NONE = 2,
USART_PARITY_SPACE = 3,
USART_PARITY_MARK = 4
};
/**
* \brief USART stop bits mode
*/
enum usart_stop_bits { USART_STOP_BITS_ONE = 0, USART_STOP_BITS_TWO = 1, USART_STOP_BITS_ONE_P_FIVE = 2 };
/**
* \brief USART character size
*/
enum usart_character_size {
USART_CHARACTER_SIZE_8BITS = 0,
USART_CHARACTER_SIZE_9BITS = 1,
USART_CHARACTER_SIZE_5BITS = 5,
USART_CHARACTER_SIZE_6BITS = 6,
USART_CHARACTER_SIZE_7BITS = 7
};
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_USART_H_INCLUDED */

270
Smol Watch Project/My Project/hal/include/hpl_usart_async.h
View file

@ -1,270 +0,0 @@
/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_USART_ASYNC_H_INCLUDED
#define _HPL_USART_ASYNC_H_INCLUDED
/**
* \addtogroup HPL USART
*
* \section hpl_usart_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include "hpl_usart.h"
#include "hpl_irq.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief USART callback types
*/
enum _usart_async_callback_type { USART_ASYNC_BYTE_SENT, USART_ASYNC_RX_DONE, USART_ASYNC_TX_DONE, USART_ASYNC_ERROR };
/**
* \brief USART device structure
*
* The USART device structure forward declaration.
*/
struct _usart_async_device;
/**
* \brief USART interrupt callbacks
*/
struct _usart_async_callbacks {
void (*tx_byte_sent)(struct _usart_async_device *device);
void (*rx_done_cb)(struct _usart_async_device *device, uint8_t data);
void (*tx_done_cb)(struct _usart_async_device *device);
void (*error_cb)(struct _usart_async_device *device);
};
/**
* \brief USART descriptor device structure
*/
struct _usart_async_device {
struct _usart_async_callbacks usart_cb;
struct _irq_descriptor irq;
void * hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize asynchronous USART
*
* This function does low level USART configuration.
*
* \param[in] device The pointer to USART device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _usart_async_init(struct _usart_async_device *const device, void *const hw);
/**
* \brief Deinitialize USART
*
* This function closes the given USART by disabling its clock.
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_deinit(struct _usart_async_device *const device);
/**
* \brief Enable usart module
*
* This function will enable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_enable(struct _usart_async_device *const device);
/**
* \brief Disable usart module
*
* This function will disable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_disable(struct _usart_async_device *const device);
/**
* \brief Calculate baud rate register value
*
* \param[in] baud Required baud rate
* \param[in] clock_rate clock frequency
* \param[in] samples The number of samples
* \param[in] mode USART mode
* \param[in] fraction A fraction value
*
* \return Calculated baud rate register value
*/
uint16_t _usart_async_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
const enum usart_baud_rate_mode mode, const uint8_t fraction);
/**
* \brief Set baud rate
*
* \param[in] device The pointer to USART device instance
* \param[in] baud_rate A baud rate to set
*/
void _usart_async_set_baud_rate(struct _usart_async_device *const device, const uint32_t baud_rate);
/**
* \brief Set data order
*
* \param[in] device The pointer to USART device instance
* \param[in] order A data order to set
*/
void _usart_async_set_data_order(struct _usart_async_device *const device, const enum usart_data_order order);
/**
* \brief Set mode
*
* \param[in] device The pointer to USART device instance
* \param[in] mode A mode to set
*/
void _usart_async_set_mode(struct _usart_async_device *const device, const enum usart_mode mode);
/**
* \brief Set parity
*
* \param[in] device The pointer to USART device instance
* \param[in] parity A parity to set
*/
void _usart_async_set_parity(struct _usart_async_device *const device, const enum usart_parity parity);
/**
* \brief Set stop bits mode
*
* \param[in] device The pointer to USART device instance
* \param[in] stop_bits A stop bits mode to set
*/
void _usart_async_set_stop_bits(struct _usart_async_device *const device, const enum usart_stop_bits stop_bits);
/**
* \brief Set character size
*
* \param[in] device The pointer to USART device instance
* \param[in] size A character size to set
*/
void _usart_async_set_character_size(struct _usart_async_device *const device, const enum usart_character_size size);
/**
* \brief Retrieve usart status
*
* \param[in] device The pointer to USART device instance
*/
uint32_t _usart_async_get_status(const struct _usart_async_device *const device);
/**
* \brief Write a byte to the given USART instance
*
* \param[in] device The pointer to USART device instance
* \param[in] data Data to write
*/
void _usart_async_write_byte(struct _usart_async_device *const device, uint8_t data);
/**
* \brief Check if USART is ready to send next byte
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the ready check.
* \retval true if the USART is ready to send next byte
* \retval false if the USART is not ready to send next byte
*/
bool _usart_async_is_byte_sent(const struct _usart_async_device *const device);
/**
* \brief Set the state of flow control pins
*
* \param[in] device The pointer to USART device instance
* \param[in] state - A state of flow control pins to set
*/
void _usart_async_set_flow_control_state(struct _usart_async_device *const device,
const union usart_flow_control_state state);
/**
* \brief Retrieve the state of flow control pins
*
* This function retrieves the of flow control pins.
*
* \return USART_FLOW_CONTROL_STATE_UNAVAILABLE.
*/
union usart_flow_control_state _usart_async_get_flow_control_state(const struct _usart_async_device *const device);
/**
* \brief Enable data register empty interrupt
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_enable_byte_sent_irq(struct _usart_async_device *const device);
/**
* \brief Enable transmission complete interrupt
*
* \param[in] device The pointer to USART device instance
*/
void _usart_async_enable_tx_done_irq(struct _usart_async_device *const device);
/**
* \brief Retrieve ordinal number of the given USART hardware instance
*
* \param[in] device The pointer to USART device instance
*
* \return The ordinal number of the given USART hardware instance
*/
uint8_t _usart_async_get_hardware_index(const struct _usart_async_device *const device);
/**
* \brief Enable/disable USART interrupt
*
* param[in] device The pointer to USART device instance
* param[in] type The type of interrupt to disable/enable if applicable
* param[in] state Enable or disable
*/
void _usart_async_set_irq_state(struct _usart_async_device *const device, const enum _usart_async_callback_type type,
const bool state);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_USART_ASYNC_H_INCLUDED */

254
Smol Watch Project/My Project/hal/include/hpl_usart_sync.h
View file

@ -1,254 +0,0 @@
/**
* \file
*
* \brief USART related functionality declaration.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#ifndef _HPL_SYNC_USART_H_INCLUDED
#define _HPL_SYNC_USART_H_INCLUDED
/**
* \addtogroup HPL USART SYNC
*
* \section hpl_usart_sync_rev Revision History
* - v1.0.0 Initial Release
*
*@{
*/
#include <hpl_usart.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \brief USART descriptor device structure
*/
struct _usart_sync_device {
void *hw;
};
/**
* \name HPL functions
*/
//@{
/**
* \brief Initialize synchronous USART
*
* This function does low level USART configuration.
*
* \param[in] device The pointer to USART device instance
* \param[in] hw The pointer to hardware instance
*
* \return Initialization status
*/
int32_t _usart_sync_init(struct _usart_sync_device *const device, void *const hw);
/**
* \brief Deinitialize USART
*
* This function closes the given USART by disabling its clock.
*
* \param[in] device The pointer to USART device instance
*/
void _usart_sync_deinit(struct _usart_sync_device *const device);
/**
* \brief Enable usart module
*
* This function will enable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_sync_enable(struct _usart_sync_device *const device);
/**
* \brief Disable usart module
*
* This function will disable the usart module
*
* \param[in] device The pointer to USART device instance
*/
void _usart_sync_disable(struct _usart_sync_device *const device);
/**
* \brief Calculate baud rate register value
*
* \param[in] baud Required baud rate
* \param[in] clock_rate clock frequency
* \param[in] samples The number of samples
* \param[in] mode USART mode
* \param[in] fraction A fraction value
*
* \return Calculated baud rate register value
*/
uint16_t _usart_sync_calculate_baud_rate(const uint32_t baud, const uint32_t clock_rate, const uint8_t samples,
const enum usart_baud_rate_mode mode, const uint8_t fraction);
/**
* \brief Set baud rate
*
* \param[in] device The pointer to USART device instance
* \param[in] baud_rate A baud rate to set
*/
void _usart_sync_set_baud_rate(struct _usart_sync_device *const device, const uint32_t baud_rate);
/**
* \brief Set data order
*
* \param[in] device The pointer to USART device instance
* \param[in] order A data order to set
*/
void _usart_sync_set_data_order(struct _usart_sync_device *const device, const enum usart_data_order order);
/**
* \brief Set mode
*
* \param[in] device The pointer to USART device instance
* \param[in] mode A mode to set
*/
void _usart_sync_set_mode(struct _usart_sync_device *const device, const enum usart_mode mode);
/**
* \brief Set parity
*
* \param[in] device The pointer to USART device instance
* \param[in] parity A parity to set
*/
void _usart_sync_set_parity(struct _usart_sync_device *const device, const enum usart_parity parity);
/**
* \brief Set stop bits mode
*
* \param[in] device The pointer to USART device instance
* \param[in] stop_bits A stop bits mode to set
*/
void _usart_sync_set_stop_bits(struct _usart_sync_device *const device, const enum usart_stop_bits stop_bits);
/**
* \brief Set character size
*
* \param[in] device The pointer to USART device instance
* \param[in] size A character size to set
*/
void _usart_sync_set_character_size(struct _usart_sync_device *const device, const enum usart_character_size size);
/**
* \brief Retrieve usart status
*
* \param[in] device The pointer to USART device instance
*/
uint32_t _usart_sync_get_status(const struct _usart_sync_device *const device);
/**
* \brief Write a byte to the given USART instance
*
* \param[in] device The pointer to USART device instance
* \param[in] data Data to write
*/
void _usart_sync_write_byte(struct _usart_sync_device *const device, uint8_t data);
/**
* \brief Read a byte from the given USART instance
*
* \param[in] device The pointer to USART device instance
* \param[in] data Data to write
*
* \return Data received via USART interface.
*/
uint8_t _usart_sync_read_byte(const struct _usart_sync_device *const device);
/**
* \brief Check if USART is ready to send next byte
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the ready check.
* \retval true if the USART is ready to send next byte
* \retval false if the USART is not ready to send next byte
*/
bool _usart_sync_is_ready_to_send(const struct _usart_sync_device *const device);
/**
* \brief Check if USART transmitter has sent the byte
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the ready check.
* \retval true if the USART transmitter has sent the byte
* \retval false if the USART transmitter has not send the byte
*/
bool _usart_sync_is_transmit_done(const struct _usart_sync_device *const device);
/**
* \brief Check if there is data received by USART
*
* \param[in] device The pointer to USART device instance
*
* \return Status of the data received check.
* \retval true if the USART has received a byte
* \retval false if the USART has not received a byte
*/
bool _usart_sync_is_byte_received(const struct _usart_sync_device *const device);
/**
* \brief Set the state of flow control pins
*
* \param[in] device The pointer to USART device instance
* \param[in] state - A state of flow control pins to set
*/
void _usart_sync_set_flow_control_state(struct _usart_sync_device *const device,
const union usart_flow_control_state state);
/**
* \brief Retrieve the state of flow control pins
*
* This function retrieves the of flow control pins.
*
* \return USART_FLOW_CONTROL_STATE_UNAVAILABLE.
*/
union usart_flow_control_state _usart_sync_get_flow_control_state(const struct _usart_sync_device *const device);
/**
* \brief Retrieve ordinal number of the given USART hardware instance
*
* \param[in] device The pointer to USART device instance
*
* \return The ordinal number of the given USART hardware instance
*/
uint8_t _usart_sync_get_hardware_index(const struct _usart_sync_device *const device);
//@}
#ifdef __cplusplus
}
#endif
/**@}*/
#endif /* _HPL_SYNC_USART_H_INCLUDED */

244
Smol Watch Project/My Project/hal/src/hal_adc_sync.c
View file

@ -1,244 +0,0 @@
/**
* \file
*
* \brief ADC functionality implementation.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
/**
* \brief Indicates HAL being compiled. Must be defined before including.
*/
#define _COMPILING_HAL
#include "hal_adc_sync.h"
#include <utils_assert.h>
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
/**
* \brief Maximum amount of ADC interface instances
*/
#define MAX_ADC_AMOUNT ADC_INST_NUM
/**
* \brief Initialize ADC
*/
int32_t adc_sync_init(struct adc_sync_descriptor *const descr, void *const hw, void *const func)
{
ASSERT(descr && hw);
return _adc_sync_init(&descr->device, hw);
}
/**
* \brief Deinitialize ADC
*/
int32_t adc_sync_deinit(struct adc_sync_descriptor *const descr)
{
ASSERT(descr);
_adc_sync_deinit(&descr->device);
return ERR_NONE;
}
/**
* \brief Enable ADC
*/
int32_t adc_sync_enable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel)
{
ASSERT(descr);
_adc_sync_enable_channel(&descr->device, channel);
return ERR_NONE;
}
/**
* \brief Disable ADC
*/
int32_t adc_sync_disable_channel(struct adc_sync_descriptor *const descr, const uint8_t channel)
{
ASSERT(descr);
_adc_sync_disable_channel(&descr->device, channel);
return ERR_NONE;
}
/*
* \brief Read data from ADC
*/
int32_t adc_sync_read_channel(struct adc_sync_descriptor *const descr, const uint8_t channel, uint8_t *const buffer,
const uint16_t length)
{
uint8_t data_size;
uint16_t offset = 0;
ASSERT(descr && buffer && length);
data_size = _adc_sync_get_data_size(&descr->device);
ASSERT(!(length % data_size));
do {
uint16_t result;
_adc_sync_convert(&descr->device);
while (!_adc_sync_is_channel_conversion_done(&descr->device, channel))
;
result = _adc_sync_read_channel_data(&descr->device, channel);
buffer[offset] = result;
if (1 < data_size) {
buffer[offset + 1] = result >> 8;
}
offset += data_size;
} while (offset < length);
return offset;
}
/**
* \brief Set ADC reference source
*/
int32_t adc_sync_set_reference(struct adc_sync_descriptor *const descr, const adc_reference_t reference)
{
ASSERT(descr);
_adc_sync_set_reference_source(&descr->device, reference);
return ERR_NONE;
}
/**
* \brief Set ADC resolution
*/
int32_t adc_sync_set_resolution(struct adc_sync_descriptor *const descr, const adc_resolution_t resolution)
{
ASSERT(descr);
_adc_sync_set_resolution(&descr->device, resolution);
return ERR_NONE;
}
/**
* \brief Set ADC input source of a channel
*/
int32_t adc_sync_set_inputs(struct adc_sync_descriptor *const descr, const adc_pos_input_t pos_input,
const adc_neg_input_t neg_input, const uint8_t channel)
{
ASSERT(descr);
_adc_sync_set_inputs(&descr->device, pos_input, neg_input, channel);
return ERR_NONE;
}
/**
* \brief Set ADC thresholds
*/
int32_t adc_sync_set_thresholds(struct adc_sync_descriptor *const descr, const adc_threshold_t low_threshold,
const adc_threshold_t up_threshold)
{
ASSERT(descr);
_adc_sync_set_thresholds(&descr->device, low_threshold, up_threshold);
return ERR_NONE;
}
/**
* \brief Set ADC gain
*/
int32_t adc_sync_set_channel_gain(struct adc_sync_descriptor *const descr, const uint8_t channel, const adc_gain_t gain)
{
ASSERT(descr);
_adc_sync_set_channel_gain(&descr->device, channel, gain);
return ERR_NONE;
}
/**
* \brief Set ADC conversion mode
*/
int32_t adc_sync_set_conversion_mode(struct adc_sync_descriptor *const descr, const enum adc_conversion_mode mode)
{
ASSERT(descr);
_adc_sync_set_conversion_mode(&descr->device, mode);
return ERR_NONE;
}
/**
* \brief Set ADC differential mode
*/
int32_t adc_sync_set_channel_differential_mode(struct adc_sync_descriptor *const descr, const uint8_t channel,
const enum adc_differential_mode mode)
{
ASSERT(descr);
_adc_sync_set_channel_differential_mode(&descr->device, channel, mode);
return ERR_NONE;
}
/**
* \brief Set ADC window mode
*/
int32_t adc_sync_set_window_mode(struct adc_sync_descriptor *const descr, const adc_window_mode_t mode)
{
ASSERT(descr);
_adc_sync_set_window_mode(&descr->device, mode);
return ERR_NONE;
}
/**
* \brief Retrieve threshold state
*/
int32_t adc_sync_get_threshold_state(const struct adc_sync_descriptor *const descr, adc_threshold_status_t *const state)
{
ASSERT(descr && state);
_adc_sync_get_threshold_state(&descr->device, state);
return ERR_NONE;
}
/**
* \brief Check if conversion is complete
*/
int32_t adc_sync_is_channel_conversion_complete(const struct adc_sync_descriptor *const descr, const uint8_t channel)
{
ASSERT(descr);
return _adc_sync_is_channel_conversion_done(&descr->device, channel);
}
/**
* \brief Retrieve the current driver version
*/
uint32_t adc_sync_get_version(void)
{
return DRIVER_VERSION;
}
//@}

66
Smol Watch Project/My Project/hal/src/hal_atomic.c
View file

@ -1,66 +0,0 @@
/**
* \file
*
* \brief Critical sections related functionality implementation.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_atomic.h"
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
/**
* \brief Disable interrupts, enter critical section
*/
void atomic_enter_critical(hal_atomic_t volatile *atomic)
{
*atomic = __get_PRIMASK();
__disable_irq();
__DMB();
}
/**
* \brief Exit atomic section
*/
void atomic_leave_critical(hal_atomic_t volatile *atomic)
{
__DMB();
__set_PRIMASK(*atomic);
}
/**
* \brief Retrieve the current driver version
*/
uint32_t atomic_get_version(void)
{
return DRIVER_VERSION;
}

643
Smol Watch Project/My Project/hal/src/hal_calendar.c
View file

@ -1,643 +0,0 @@
/**
* \file
*
* \brief Generic CALENDAR functionality implementation.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_calendar.h"
#include <utils.h>
#include <utils_assert.h>
#include <hal_atomic.h>
#define CALENDAR_VERSION 0x00000001u
#define SECS_IN_LEAP_YEAR 31622400
#define SECS_IN_NON_LEAP_YEAR 31536000
#define SECS_IN_31DAYS 2678400
#define SECS_IN_30DAYS 2592000
#define SECS_IN_29DAYS 2505600
#define SECS_IN_28DAYS 2419200
#define SECS_IN_DAY 86400
#define SECS_IN_HOUR 3600
#define SECS_IN_MINUTE 60
#define DEFAULT_BASE_YEAR 1970
#define SET_ALARM_BUSY 1
#define PROCESS_ALARM_BUSY 2
/** \brief leap year check
* \retval false not leap year.
* \retval true leap year.
*/
static bool leap_year(uint16_t year)
{
if (year & 3) {
return false;
} else {
return true;
}
}
/** \brief calculate the seconds in specified year/month
* \retval 0 month error.
*/
static uint32_t get_secs_in_month(uint32_t year, uint8_t month)
{
uint32_t sec_in_month = 0;
if (leap_year(year)) {
switch (month) {
case 1:
case 3:
case 5:
case 7:
case 8:
case 10:
case 12:
sec_in_month = SECS_IN_31DAYS;
break;
case 2:
sec_in_month = SECS_IN_29DAYS;
break;
case 4:
case 6:
case 9:
case 11:
sec_in_month = SECS_IN_30DAYS;
break;
default:
break;
}
} else {
switch (month) {
case 1:
case 3:
case 5:
case 7:
case 8:
case 10:
case 12:
sec_in_month = SECS_IN_31DAYS;
break;
case 2:
sec_in_month = SECS_IN_28DAYS;
break;
case 4:
case 6:
case 9:
case 11:
sec_in_month = SECS_IN_30DAYS;
break;
default:
break;
}
}
return sec_in_month;
}
/** \brief convert timestamp to date/time
*/
static int32_t convert_timestamp_to_datetime(struct calendar_descriptor *const calendar, uint32_t ts,
struct calendar_date_time *dt)
{
uint32_t tmp, sec_in_year, sec_in_month;
uint32_t tmp_year = calendar->base_year;
uint8_t tmp_month = 1;
uint8_t tmp_day = 1;
uint8_t tmp_hour = 0;
uint8_t tmp_minutes = 0;
tmp = ts;
/* Find year */
while (true) {
sec_in_year = leap_year(tmp_year) ? SECS_IN_LEAP_YEAR : SECS_IN_NON_LEAP_YEAR;
if (tmp >= sec_in_year) {
tmp -= sec_in_year;
tmp_year++;
} else {
break;
}
}
/* Find month of year */
while (true) {
sec_in_month = get_secs_in_month(tmp_year, tmp_month);
if (tmp >= sec_in_month) {
tmp -= sec_in_month;
tmp_month++;
} else {
break;
}
}
/* Find day of month */
while (true) {
if (tmp >= SECS_IN_DAY) {
tmp -= SECS_IN_DAY;
tmp_day++;
} else {
break;
}
}
/* Find hour of day */
while (true) {
if (tmp >= SECS_IN_HOUR) {
tmp -= SECS_IN_HOUR;
tmp_hour++;
} else {
break;
}
}
/* Find minute in hour */
while (true) {
if (tmp >= SECS_IN_MINUTE) {
tmp -= SECS_IN_MINUTE;
tmp_minutes++;
} else {
break;
}
}
dt->date.year = tmp_year;
dt->date.month = tmp_month;
dt->date.day = tmp_day;
dt->time.hour = tmp_hour;
dt->time.min = tmp_minutes;
dt->time.sec = tmp;
return ERR_NONE;
}
/** \brief convert date/time to timestamp
* \return timestamp
*/
static uint32_t convert_datetime_to_timestamp(struct calendar_descriptor *const calendar, struct calendar_date_time *dt)
{
uint32_t tmp = 0;
uint32_t i = 0;
uint8_t year, month, day, hour, minutes, seconds;
year = dt->date.year - calendar->base_year;
month = dt->date.month;
day = dt->date.day;
hour = dt->time.hour;
minutes = dt->time.min;
seconds = dt->time.sec;
/* tot up year field */
for (i = 0; i < year; ++i) {
if (leap_year(calendar->base_year + i)) {
tmp += SECS_IN_LEAP_YEAR;
} else {
tmp += SECS_IN_NON_LEAP_YEAR;
}
}
/* tot up month field */
for (i = 1; i < month; ++i) {
tmp += get_secs_in_month(dt->date.year, i);
}
/* tot up day/hour/minute/second fields */
tmp += (day - 1) * SECS_IN_DAY;
tmp += hour * SECS_IN_HOUR;
tmp += minutes * SECS_IN_MINUTE;
tmp += seconds;
return tmp;
}
/** \brief calibrate timestamp to make desired timestamp ahead of current timestamp
*/
static void calibrate_timestamp(struct calendar_descriptor *const calendar, struct calendar_alarm *alarm,
struct calendar_alarm *current_dt)
{
uint32_t alarm_ts;
uint32_t current_ts = current_dt->cal_alarm.timestamp;
alarm_ts = alarm->cal_alarm.timestamp;
/* calibrate timestamp */
switch (alarm->cal_alarm.option) {
case CALENDAR_ALARM_MATCH_SEC:
if (alarm_ts <= current_ts) {
alarm_ts += SECS_IN_MINUTE;
}
break;
case CALENDAR_ALARM_MATCH_MIN:
if (alarm_ts <= current_ts) {
alarm_ts += SECS_IN_HOUR;
}
break;
case CALENDAR_ALARM_MATCH_HOUR:
if (alarm_ts <= current_ts) {
alarm_ts += SECS_IN_DAY;
}
break;
case CALENDAR_ALARM_MATCH_DAY:
if (alarm_ts <= current_ts) {
alarm_ts += get_secs_in_month(current_dt->cal_alarm.datetime.date.year,
current_dt->cal_alarm.datetime.date.month);
}
break;
case CALENDAR_ALARM_MATCH_MONTH:
if (alarm_ts <= current_ts) {
if (leap_year(current_dt->cal_alarm.datetime.date.year)) {
alarm_ts += SECS_IN_LEAP_YEAR;
} else {
alarm_ts += SECS_IN_NON_LEAP_YEAR;
}
}
break;
/* do nothing for year match */
case CALENDAR_ALARM_MATCH_YEAR:
default:
break;
}
/* desired timestamp after calibration */
alarm->cal_alarm.timestamp = alarm_ts;
}
/** \brief complete alarm to absolute date/time, then fill up the timestamp
*/
static void fill_alarm(struct calendar_descriptor *const calendar, struct calendar_alarm *alarm)
{
struct calendar_alarm current_dt;
uint32_t tmp, current_ts;
/* get current date/time */
current_ts = _calendar_get_counter(&calendar->device);
convert_timestamp_to_datetime(calendar, current_ts, &current_dt.cal_alarm.datetime);
current_dt.cal_alarm.timestamp = current_ts;
/* complete alarm */
switch (alarm->cal_alarm.option) {
case CALENDAR_ALARM_MATCH_SEC:
alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
alarm->cal_alarm.datetime.date.day = current_dt.cal_alarm.datetime.date.day;
alarm->cal_alarm.datetime.time.hour = current_dt.cal_alarm.datetime.time.hour;
alarm->cal_alarm.datetime.time.min = current_dt.cal_alarm.datetime.time.min;
break;
case CALENDAR_ALARM_MATCH_MIN:
alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
alarm->cal_alarm.datetime.date.day = current_dt.cal_alarm.datetime.date.day;
alarm->cal_alarm.datetime.time.hour = current_dt.cal_alarm.datetime.time.hour;
break;
case CALENDAR_ALARM_MATCH_HOUR:
alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
alarm->cal_alarm.datetime.date.day = current_dt.cal_alarm.datetime.date.day;
break;
case CALENDAR_ALARM_MATCH_DAY:
alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
alarm->cal_alarm.datetime.date.month = current_dt.cal_alarm.datetime.date.month;
break;
case CALENDAR_ALARM_MATCH_MONTH:
alarm->cal_alarm.datetime.date.year = current_dt.cal_alarm.datetime.date.year;
break;
case CALENDAR_ALARM_MATCH_YEAR:
break;
default:
break;
}
/* fill up the timestamp */
tmp = convert_datetime_to_timestamp(calendar, &alarm->cal_alarm.datetime);
alarm->cal_alarm.timestamp = tmp;
/* calibrate the timestamp */
calibrate_timestamp(calendar, alarm, &current_dt);
convert_timestamp_to_datetime(calendar, alarm->cal_alarm.timestamp, &alarm->cal_alarm.datetime);
}
/** \brief add new alarm into the list in ascending order
*/
static int32_t calendar_add_new_alarm(struct list_descriptor *list, struct calendar_alarm *alarm)
{
struct calendar_descriptor *calendar = CONTAINER_OF(list, struct calendar_descriptor, alarms);
struct calendar_alarm * head, *it, *prev = NULL;
/*get the head of alarms list*/
head = (struct calendar_alarm *)list_get_head(list);
/*if head is null, insert new alarm as head*/
if (!head) {
list_insert_as_head(list, alarm);
_calendar_set_comp(&calendar->device, alarm->cal_alarm.timestamp);
return ERR_NONE;
}
/*insert the new alarm in accending order, the head will be invoked firstly */
for (it = head; it; it = (struct calendar_alarm *)list_get_next_element(it)) {
if (alarm->cal_alarm.timestamp <= it->cal_alarm.timestamp) {
break;
}
prev = it;
}
/*insert new alarm into the list */
if (it == head) {
list_insert_as_head(list, alarm);
/*get the head and set it into register*/
_calendar_set_comp(&calendar->device, alarm->cal_alarm.timestamp);
} else {
list_insert_after(prev, alarm);
}
return ERR_NONE;
}
/** \brief callback for alarm
*/
static void calendar_alarm(struct calendar_dev *const dev)
{
struct calendar_descriptor *calendar = CONTAINER_OF(dev, struct calendar_descriptor, device);
struct calendar_alarm *head, *it, current_dt;
if ((calendar->flags & SET_ALARM_BUSY) || (calendar->flags & PROCESS_ALARM_BUSY)) {
calendar->flags |= PROCESS_ALARM_BUSY;
return;
}
/* get current timestamp */
current_dt.cal_alarm.timestamp = _calendar_get_counter(dev);
/* get the head */
head = (struct calendar_alarm *)list_get_head(&calendar->alarms);
ASSERT(head);
/* remove all alarms and invoke them*/
for (it = head; it; it = (struct calendar_alarm *)list_get_head(&calendar->alarms)) {
/* check the timestamp with current timestamp*/
if (it->cal_alarm.timestamp <= current_dt.cal_alarm.timestamp) {
list_remove_head(&calendar->alarms);
it->callback(calendar);
if (it->cal_alarm.mode == REPEAT) {
calibrate_timestamp(calendar, it, &current_dt);
convert_timestamp_to_datetime(calendar, it->cal_alarm.timestamp, &it->cal_alarm.datetime);
calendar_add_new_alarm(&calendar->alarms, it);
}
} else {
break;
}
}
/*if no alarm in the list, register null */
if (!it) {
_calendar_register_callback(&calendar->device, NULL);
return;
}
/*put the new head into register */
_calendar_set_comp(&calendar->device, it->cal_alarm.timestamp);
}
/** \brief Initialize Calendar
*/
int32_t calendar_init(struct calendar_descriptor *const calendar, const void *hw)
{
int32_t ret = 0;
/* Sanity check arguments */
ASSERT(calendar);
if (calendar->device.hw == hw) {
/* Already initialized with current configuration */
return ERR_NONE;
} else if (calendar->device.hw != NULL) {
/* Initialized with another configuration */
return ERR_ALREADY_INITIALIZED;
}
calendar->device.hw = (void *)hw;
ret = _calendar_init(&calendar->device);
calendar->base_year = DEFAULT_BASE_YEAR;
return ret;
}
/** \brief Reset the Calendar
*/
int32_t calendar_deinit(struct calendar_descriptor *const calendar)
{
/* Sanity check arguments */
ASSERT(calendar);
if (calendar->device.hw == NULL) {
return ERR_NOT_INITIALIZED;
}
_calendar_deinit(&calendar->device);
calendar->device.hw = NULL;
return ERR_NONE;
}
/** \brief Enable the Calendar
*/
int32_t calendar_enable(struct calendar_descriptor *const calendar)
{
/* Sanity check arguments */
ASSERT(calendar);
_calendar_enable(&calendar->device);
return ERR_NONE;
}
/** \brief Disable the Calendar
*/
int32_t calendar_disable(struct calendar_descriptor *const calendar)
{
/* Sanity check arguments */
ASSERT(calendar);
_calendar_disable(&calendar->device);
return ERR_NONE;
}
/** \brief Set base year for calendar
*/
int32_t calendar_set_baseyear(struct calendar_descriptor *const calendar, const uint32_t p_base_year)
{
/* Sanity check arguments */
ASSERT(calendar);
calendar->base_year = p_base_year;
return ERR_NONE;
}
/** \brief Set time for calendar
*/
int32_t calendar_set_time(struct calendar_descriptor *const calendar, struct calendar_time *const p_calendar_time)
{
struct calendar_date_time dt;
uint32_t current_ts, new_ts;
/* Sanity check arguments */
ASSERT(calendar);
/* convert time to timestamp */
current_ts = _calendar_get_counter(&calendar->device);
convert_timestamp_to_datetime(calendar, current_ts, &dt);
dt.time.sec = p_calendar_time->sec;
dt.time.min = p_calendar_time->min;
dt.time.hour = p_calendar_time->hour;
new_ts = convert_datetime_to_timestamp(calendar, &dt);
_calendar_set_counter(&calendar->device, new_ts);
return ERR_NONE;
}
/** \brief Set date for calendar
*/
int32_t calendar_set_date(struct calendar_descriptor *const calendar, struct calendar_date *const p_calendar_date)
{
struct calendar_date_time dt;
uint32_t current_ts, new_ts;
/* Sanity check arguments */
ASSERT(calendar);
/* convert date to timestamp */
current_ts = _calendar_get_counter(&calendar->device);
convert_timestamp_to_datetime(calendar, current_ts, &dt);
dt.date.day = p_calendar_date->day;
dt.date.month = p_calendar_date->month;
dt.date.year = p_calendar_date->year;
new_ts = convert_datetime_to_timestamp(calendar, &dt);
_calendar_set_counter(&calendar->device, new_ts);
return ERR_NONE;
}
/** \brief Get date/time for calendar
*/
int32_t calendar_get_date_time(struct calendar_descriptor *const calendar, struct calendar_date_time *const date_time)
{
uint32_t current_ts;
/* Sanity check arguments */
ASSERT(calendar);
/* convert current timestamp to date/time */
current_ts = _calendar_get_counter(&calendar->device);
convert_timestamp_to_datetime(calendar, current_ts, date_time);
return ERR_NONE;
}
/** \brief Set alarm for calendar
*/
int32_t calendar_set_alarm(struct calendar_descriptor *const calendar, struct calendar_alarm *const alarm,
calendar_cb_alarm_t callback)
{
struct calendar_alarm *head;
/* Sanity check arguments */
ASSERT(calendar);
ASSERT(alarm);
alarm->callback = callback;
fill_alarm(calendar, alarm);
calendar->flags |= SET_ALARM_BUSY;
head = (struct calendar_alarm *)list_get_head(&calendar->alarms);
if (head != NULL) {
/* already added */
if (is_list_element(&calendar->alarms, alarm)) {
if (callback == NULL) {
/* remove alarm */
list_delete_element(&calendar->alarms, alarm);
if (!list_get_head(&calendar->alarms)) {
_calendar_register_callback(&calendar->device, NULL);
}
} else {
/* re-add */
list_delete_element(&calendar->alarms, alarm);
calendar_add_new_alarm(&calendar->alarms, alarm);
}
} else if (callback != NULL) {
calendar_add_new_alarm(&calendar->alarms, alarm);
}
calendar->flags &= ~SET_ALARM_BUSY;
if (calendar->flags & PROCESS_ALARM_BUSY) {
CRITICAL_SECTION_ENTER()
calendar->flags &= ~PROCESS_ALARM_BUSY;
_calendar_set_irq(&calendar->device);
CRITICAL_SECTION_LEAVE()
}
} else if (callback != NULL) {
/* if head is NULL, Register callback*/
_calendar_register_callback(&calendar->device, calendar_alarm);
calendar_add_new_alarm(&calendar->alarms, alarm);
}
calendar->flags &= ~SET_ALARM_BUSY;
return ERR_NONE;
}
/** \brief Retrieve driver version
* \return Current driver version
*/
uint32_t calendar_get_version(void)
{
return CALENDAR_VERSION;
}

80
Smol Watch Project/My Project/hal/src/hal_delay.c
View file

@ -1,80 +0,0 @@
/**
* \file
*
* \brief HAL delay related functionality implementation.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hpl_irq.h>
#include <hpl_reset.h>
#include <hpl_sleep.h>
#include "hal_delay.h"
#include <hpl_delay.h>
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
/**
* \brief The pointer to a hardware instance used by the driver.
*/
static void *hardware;
/**
* \brief Initialize Delay driver
*/
void delay_init(void *const hw)
{
_delay_init(hardware = hw);
}
/**
* \brief Perform delay in us
*/
void delay_us(const uint16_t us)
{
_delay_cycles(hardware, _get_cycles_for_us(us));
}
/**
* \brief Perform delay in ms
*/
void delay_ms(const uint16_t ms)
{
_delay_cycles(hardware, _get_cycles_for_ms(ms));
}
/**
* \brief Retrieve the current driver version
*/
uint32_t delay_get_version(void)
{
return DRIVER_VERSION;
}

188
Smol Watch Project/My Project/hal/src/hal_ext_irq.c
View file

@ -1,188 +0,0 @@
/**
* \file
*
* \brief External interrupt functionality imkplementation.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_ext_irq.h"
#define EXT_IRQ_AMOUNT 3
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
/**
* \brief External IRQ struct
*/
struct ext_irq {
ext_irq_cb_t cb;
uint32_t pin;
};
/* Remove KEIL compiling error in case no IRQ line selected */
#if EXT_IRQ_AMOUNT == 0
#undef EXT_IRQ_AMOUNT
#define EXT_IRQ_AMOUNT 1
#endif
/**
* \brief Array of external IRQs callbacks
*/
static struct ext_irq ext_irqs[EXT_IRQ_AMOUNT];
static void process_ext_irq(const uint32_t pin);
/**
* \brief Initialize external irq component if any
*/
int32_t ext_irq_init(void)
{
uint16_t i;
for (i = 0; i < EXT_IRQ_AMOUNT; i++) {
ext_irqs[i].pin = 0xFFFFFFFF;
ext_irqs[i].cb = NULL;
}
return _ext_irq_init(process_ext_irq);
}
/**
* \brief Deinitialize external irq if any
*/
int32_t ext_irq_deinit(void)
{
return _ext_irq_deinit();
}
/**
* \brief Register callback for the given external interrupt
*/
int32_t ext_irq_register(const uint32_t pin, ext_irq_cb_t cb)
{
uint8_t i = 0, j = 0;
bool found = false;
for (; i < EXT_IRQ_AMOUNT; i++) {
if (ext_irqs[i].pin == pin) {
ext_irqs[i].cb = cb;
found = true;
break;
}
}
if (NULL == cb) {
if (!found) {
return ERR_INVALID_ARG;
}
return _ext_irq_enable(pin, false);
}
if (!found) {
for (i = 0; i < EXT_IRQ_AMOUNT; i++) {
if (NULL == ext_irqs[i].cb) {
ext_irqs[i].cb = cb;
ext_irqs[i].pin = pin;
found = true;
break;
}
}
for (; (j < EXT_IRQ_AMOUNT) && (i < EXT_IRQ_AMOUNT); j++) {
if ((ext_irqs[i].pin < ext_irqs[j].pin) && (ext_irqs[j].pin != 0xFFFFFFFF)) {
struct ext_irq tmp = ext_irqs[j];
ext_irqs[j] = ext_irqs[i];
ext_irqs[i] = tmp;
}
}
}
if (!found) {
return ERR_INVALID_ARG;
}
return _ext_irq_enable(pin, true);
}
/**
* \brief Enable external irq
*/
int32_t ext_irq_enable(const uint32_t pin)
{
return _ext_irq_enable(pin, true);
}
/**
* \brief Disable external irq
*/
int32_t ext_irq_disable(const uint32_t pin)
{
return _ext_irq_enable(pin, false);
}
/**
* \brief Retrieve the current driver version
*/
uint32_t ext_irq_get_version(void)
{
return DRIVER_VERSION;
}
/**
* \brief Interrupt processing routine
*
* \param[in] pin The pin which triggered the interrupt
*/
static void process_ext_irq(const uint32_t pin)
{
uint8_t lower = 0, middle, upper = EXT_IRQ_AMOUNT;
while (upper >= lower) {
middle = (upper + lower) >> 1;
if (middle >= EXT_IRQ_AMOUNT) {
return;
}
if (ext_irqs[middle].pin == pin) {
if (ext_irqs[middle].cb) {
ext_irqs[middle].cb();
}
return;
}
if (ext_irqs[middle].pin < pin) {
lower = middle + 1;
} else {
upper = middle - 1;
}
}
}

44
Smol Watch Project/My Project/hal/src/hal_gpio.c
View file

@ -1,44 +0,0 @@
/**
* \file
*
* \brief Port
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_gpio.h"
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
uint32_t gpio_get_version(void)
{
return DRIVER_VERSION;
}

258
Smol Watch Project/My Project/hal/src/hal_i2c_m_sync.c
View file

@ -1,258 +0,0 @@
/**
* \file
*
* \brief I/O I2C related functionality implementation.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hal_i2c_m_sync.h>
#include <utils.h>
#include <utils_assert.h>
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
/**
* \brief Sync version of I2C I/O read
*/
static int32_t i2c_m_sync_read(struct io_descriptor *io, uint8_t *buf, const uint16_t n)
{
struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io);
struct _i2c_m_msg msg;
int32_t ret;
msg.addr = i2c->slave_addr;
msg.len = n;
msg.flags = I2C_M_STOP | I2C_M_RD;
msg.buffer = buf;
ret = _i2c_m_sync_transfer(&i2c->device, &msg);
if (ret) {
return ret;
}
return n;
}
/**
* \brief Sync version of I2C I/O write
*/
static int32_t i2c_m_sync_write(struct io_descriptor *io, const uint8_t *buf, const uint16_t n)
{
struct i2c_m_sync_desc *i2c = CONTAINER_OF(io, struct i2c_m_sync_desc, io);
struct _i2c_m_msg msg;
int32_t ret;
msg.addr = i2c->slave_addr;
msg.len = n;
msg.flags = I2C_M_STOP;
msg.buffer = (uint8_t *)buf;
ret = _i2c_m_sync_transfer(&i2c->device, &msg);
if (ret) {
return ret;
}
return n;
}
/**
* \brief Sync version of i2c initialize
*/
int32_t i2c_m_sync_init(struct i2c_m_sync_desc *i2c, void *hw)
{
int32_t init_status;
ASSERT(i2c);
init_status = _i2c_m_sync_init(&i2c->device, hw);
if (init_status) {
return init_status;
}
/* Init I/O */
i2c->io.read = i2c_m_sync_read;
i2c->io.write = i2c_m_sync_write;
return ERR_NONE;
}
/**
* \brief deinitialize
*/
int32_t i2c_m_sync_deinit(struct i2c_m_sync_desc *i2c)
{
int32_t status;
ASSERT(i2c);
status = _i2c_m_sync_deinit(&i2c->device);
if (status) {
return status;
}
i2c->io.read = NULL;
i2c->io.write = NULL;
return ERR_NONE;
}
/**
* \brief Sync version of i2c enable
*/
int32_t i2c_m_sync_enable(struct i2c_m_sync_desc *i2c)
{
return _i2c_m_sync_enable(&i2c->device);
}
/**
* \brief Sync version of i2c disable
*/
int32_t i2c_m_sync_disable(struct i2c_m_sync_desc *i2c)
{
return _i2c_m_sync_disable(&i2c->device);
}
/**
* \brief Sync version of i2c set slave address
*/
int32_t i2c_m_sync_set_slaveaddr(struct i2c_m_sync_desc *i2c, int16_t addr, int32_t addr_len)
{
return i2c->slave_addr = (addr & 0x3ff) | (addr_len & I2C_M_TEN);
}
/**
* \brief Sync version of i2c set baudrate
*/
int32_t i2c_m_sync_set_baudrate(struct i2c_m_sync_desc *i2c, uint32_t clkrate, uint32_t baudrate)
{
return _i2c_m_sync_set_baudrate(&i2c->device, clkrate, baudrate);
}
/**
* \brief Sync version of i2c write command
*/
int32_t i2c_m_sync_cmd_write(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length)
{
struct _i2c_m_msg msg;
int32_t ret;
msg.addr = i2c->slave_addr;
msg.len = 1;
msg.flags = 0;
msg.buffer = &reg;
ret = _i2c_m_sync_transfer(&i2c->device, &msg);
if (ret != 0) {
/* error occurred */
return ret;
}
msg.flags = I2C_M_STOP;
msg.buffer = buffer;
msg.len = length;
ret = _i2c_m_sync_transfer(&i2c->device, &msg);
if (ret != 0) {
/* error occurred */
return ret;
}
return ERR_NONE;
}
/**
* \brief Sync version of i2c read command
*/
int32_t i2c_m_sync_cmd_read(struct i2c_m_sync_desc *i2c, uint8_t reg, uint8_t *buffer, uint8_t length)
{
struct _i2c_m_msg msg;
int32_t ret;
msg.addr = i2c->slave_addr;
msg.len = 1;
msg.flags = 0;
msg.buffer = &reg;
ret = _i2c_m_sync_transfer(&i2c->device, &msg);
if (ret != 0) {
/* error occurred */
return ret;
}
msg.flags = I2C_M_STOP | I2C_M_RD;
msg.buffer = buffer;
msg.len = length;
ret = _i2c_m_sync_transfer(&i2c->device, &msg);
if (ret != 0) {
/* error occurred */
return ret;
}
return ERR_NONE;
}
/**
* \brief Sync version of i2c transfer command
*/
int32_t i2c_m_sync_transfer(struct i2c_m_sync_desc *const i2c, struct _i2c_m_msg *msg)
{
return _i2c_m_sync_transfer(&i2c->device, msg);
}
/**
* \brief Sync version of i2c send stop condition command
*/
int32_t i2c_m_sync_send_stop(struct i2c_m_sync_desc *const i2c)
{
return _i2c_m_sync_send_stop(&i2c->device);
}
/**
* \brief Retrieve I/O descriptor
*/
int32_t i2c_m_sync_get_io_descriptor(struct i2c_m_sync_desc *const i2c, struct io_descriptor **io)
{
*io = &i2c->io;
return ERR_NONE;
}
/**
* \brief Retrieve the current driver version
*/
uint32_t i2c_m_sync_get_version(void)
{
return DRIVER_VERSION;
}

47
Smol Watch Project/My Project/hal/src/hal_init.c
View file

@ -1,47 +0,0 @@
/**
* \file
*
* \brief HAL initialization related functionality implementation.
*
* Copyright (c) 2014-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_init.h"
/**
* \brief Driver version
*/
#define HAL_INIT_VERSION 0x00000001u
/**
* \brief Retrieve the current driver version
*/
uint32_t init_get_version(void)
{
return HAL_INIT_VERSION;
}

63
Smol Watch Project/My Project/hal/src/hal_io.c
View file

@ -1,63 +0,0 @@
/**
* \file
*
* \brief I/O functionality implementation.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include <hal_io.h>
#include <utils_assert.h>
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
uint32_t io_get_version(void)
{
return DRIVER_VERSION;
}
/**
* \brief I/O write interface
*/
int32_t io_write(struct io_descriptor *const io_descr, const uint8_t *const buf, const uint16_t length)
{
ASSERT(io_descr && buf);
return io_descr->write(io_descr, buf, length);
}
/**
* \brief I/O read interface
*/
int32_t io_read(struct io_descriptor *const io_descr, uint8_t *const buf, const uint16_t length)
{
ASSERT(io_descr && buf);
return io_descr->read(io_descr, buf, length);
}

159
Smol Watch Project/My Project/hal/src/hal_pwm.c
View file

@ -1,159 +0,0 @@
/**
* \file
*
* \brief PWM functionality implementation.
*
* Copyright (c) 2015-2018 Microchip Technology Inc. and its subsidiaries.
*
* \asf_license_start
*
* \page License
*
* Subject to your compliance with these terms, you may use Microchip
* software and any derivatives exclusively with Microchip products.
* It is your responsibility to comply with third party license terms applicable
* to your use of third party software (including open source software) that
* may accompany Microchip software.
*
* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
*
* \asf_license_stop
*
*/
#include "hal_pwm.h"
#include <utils_assert.h>
#include <utils.h>
/**
* \brief Driver version
*/
#define DRIVER_VERSION 0x00000001u
static void pwm_period_expired(struct _pwm_device *device);
static void pwm_detect_fault(struct _pwm_device *device);
/**
* \brief Initialize pwm
*/
int32_t pwm_init(struct pwm_descriptor *const descr, void *const hw, struct _pwm_hpl_interface *const func)
{
ASSERT(descr && hw);
_pwm_init(&descr->device, hw);
descr->device.callback.pwm_period_cb = pwm_period_expired;
descr->device.callback.pwm_error_cb = pwm_detect_fault;
return ERR_NONE;
}
/**
* \brief Deinitialize pwm
*/
int32_t pwm_deinit(struct pwm_descriptor *const descr)
{
ASSERT(descr);
_pwm_deinit(&descr->device);
return ERR_NONE;
}
/**
* \brief Start pwm
*/
int32_t pwm_enable(struct pwm_descriptor *const descr)
{
ASSERT(descr);
if (_pwm_is_enabled(&descr->device)) {
return ERR_DENIED;
}
_pwm_enable(&descr->device);
return ERR_NONE;
}
/**
* \brief Stop pwm
*/
int32_t pwm_disable(struct pwm_descriptor *const descr)
{
ASSERT(descr);
if (!_pwm_is_enabled(&descr->device)) {
return ERR_DENIED;
}
_pwm_disable(&descr->device);
return ERR_NONE;
}
/**
* \brief Register PWM callback
*/
int32_t pwm_register_callback(struct pwm_descriptor *const descr, enum pwm_callback_type type, pwm_cb_t cb)
{
switch (type) {
case PWM_PERIOD_CB:
descr->pwm_cb.period = cb;
break;
case PWM_ERROR_CB:
descr->pwm_cb.error = cb;
break;
default:
return ERR_INVALID_ARG;
}
ASSERT(descr);
_pwm_set_irq_state(&descr->device, (enum _pwm_callback_type)type, NULL != cb);
return ERR_NONE;
}
/**
* \brief Change PWM parameter
*/
int32_t pwm_set_parameters(struct pwm_descriptor *const descr, const pwm_period_t period, const pwm_period_t duty_cycle)
{
ASSERT(descr);
_pwm_set_param(&descr->device, period, duty_cycle);
return ERR_NONE;
}
/**
* \brief Retrieve the current driver version
*/
uint32_t pwm_get_version(void)
{
return DRIVER_VERSION;
}
/**
* \internal Process interrupts caused by period experied
*/
static void pwm_period_expired(struct _pwm_device *device)
{
struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device);
if (descr->pwm_cb.period) {
descr->pwm_cb.period(descr);
}
}
/**
* \internal Process interrupts caused by pwm fault
*/
static void pwm_detect_fault(struct _pwm_device *device)
{
struct pwm_descriptor *const descr = CONTAINER_OF(device, struct pwm_descriptor, device);
if (descr->pwm_cb.error) {
descr->pwm_cb.error(descr);
}
}

Some files were not shown because too many files have changed in this diff Show more