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getting the sensor watch dev board working

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This commit is contained in:
Joey Castillo 2021-10-19 10:14:24 -04:00
parent 6210e1c233
commit 52c5747d2e
6 changed files with 28 additions and 12 deletions
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12
boards/OSO-MISC-21-013/pins.h → boards/OSO-FEAL-A1-00/pins.h
View file

@ -19,14 +19,14 @@
// LEDs
#define WATCH_INVERT_LED_POLARITY
#define RED GPIO(GPIO_PORTB, 22)
#define WATCH_RED_TCC_PINMUX PINMUX_PB22F_TCC0_WO2
#define WATCH_RED_TCC_CHANNEL 2
#define RED GPIO(GPIO_PORTA, 4)
#define WATCH_RED_TCC_CHANNEL 0
#define WATCH_RED_TCC_PINMUX PINMUX_PA04E_TCC0_WO0
#ifdef WATCH_SWAP_LED_PINS
#define GREEN GPIO(GPIO_PORTA, 4)
#define WATCH_GREEN_TCC_CHANNEL 0
#define WATCH_GREEN_TCC_PINMUX PINMUX_PA04E_TCC0_WO0
#define GREEN GPIO(GPIO_PORTB, 22)
#define WATCH_GREEN_TCC_CHANNEL 2
#define WATCH_GREEN_TCC_PINMUX PINMUX_PB22F_TCC0_WO2
#else
#define GREEN GPIO(GPIO_PORTB, 23)
#define WATCH_GREEN_TCC_CHANNEL 3

4
make.mk
View file

@ -116,3 +116,7 @@ DEFINES += \
ifeq ($(LED), BLUE)
CFLAGS += -DWATCH_SWAP_LED_PINS
endif
ifeq ($(BOARD), OSO-FEAL-A1-00)
CFLAGS += -DCRYSTALLESS
endif

7
watch-library/config/hpl_eic_config.h
View file

@ -271,7 +271,7 @@
// <i> Indicates whether the external interrupt 5 filter is enabled or not
// <id> eic_arch_filten5
#ifndef CONF_EIC_FILTEN5
#define CONF_EIC_FILTEN5 0
#define CONF_EIC_FILTEN5 1
#endif
// <q> External Interrupt 5 Event Output Enable
@ -723,7 +723,12 @@
// </e>
// my god this is a hack. need to refactor this out of ASF and into our driver. - joey 10/19
#ifdef CRYSTALLESS
#define CONFIG_EIC_EXTINT_MAP {2, PIN_PA02}, {5, PIN_PB05}, {7, PIN_PA07},
#else
#define CONFIG_EIC_EXTINT_MAP {2, PIN_PA02}, {6, PIN_PA22}, {7, PIN_PA23},
#endif
// <<< end of configuration section >>>

5
watch-library/config/hpl_gclk_config.h
View file

@ -248,9 +248,14 @@
// <i> This defines the clock source for generic clock generator 3
// <id> gclk_gen_3_oscillator
#ifndef CONF_GCLK_GEN_3_SOURCE
#ifdef CRYSTALLESS
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_OSCULP32K
#else
#define CONF_GCLK_GEN_3_SOURCE GCLK_GENCTRL_SRC_XOSC32K
#endif
#endif
// <q> Run in Standby
// <i> Indicates whether Run in Standby is enabled or not
// <id> gclk_arch_gen_3_runstdby

4
watch-library/config/hpl_osc32kctrl_config.h
View file

@ -17,8 +17,12 @@
// <i> This defines the clock source for RTC
// <id> rtc_source_oscillator
#ifndef CONF_RTCCTRL_SRC
#ifdef CRYSTALLESS
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_OSCULP32K
#else
#define CONF_RTCCTRL_SRC GCLK_GENCTRL_SRC_XOSC32K
#endif
#endif
// <q> Use 1 kHz output
// <id> rtc_1khz_selection

8
watch-library/watch/watch_extint.c
View file

@ -65,18 +65,14 @@ void watch_register_interrupt_callback(const uint8_t pin, ext_irq_cb_t callback,
sense_pos = 4 * (WATCH_A4_EIC_CHANNEL % 8);
break;
case BTN_ALARM:
// for the buttons, we need an internal pull-down.
gpio_set_pin_pull_mode(pin, GPIO_PULL_DOWN);
config_index = (WATCH_BTN_ALARM_EIC_CHANNEL > 7) ? 1 : 0;
sense_pos = 4 * (WATCH_BTN_ALARM_EIC_CHANNEL % 8);
break;
case BTN_LIGHT:
gpio_set_pin_pull_mode(pin, GPIO_PULL_DOWN);
config_index = (WATCH_BTN_LIGHT_EIC_CHANNEL > 7) ? 1 : 0;
sense_pos = 4 * (WATCH_BTN_LIGHT_EIC_CHANNEL % 8);
break;
case BTN_MODE:
gpio_set_pin_pull_mode(pin, GPIO_PULL_DOWN);
config_index = (WATCH_BTN_MODE_EIC_CHANNEL > 7) ? 1 : 0;
sense_pos = 4 * (WATCH_BTN_MODE_EIC_CHANNEL % 8);
break;
@ -85,7 +81,6 @@ void watch_register_interrupt_callback(const uint8_t pin, ext_irq_cb_t callback,
}
gpio_set_pin_direction(pin, GPIO_DIRECTION_IN);
gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_A);
// EIC configuration register is enable-protected, so we have to disable it first...
if (hri_eic_get_CTRLA_reg(EIC, EIC_CTRLA_ENABLE)) {
@ -98,6 +93,9 @@ void watch_register_interrupt_callback(const uint8_t pin, ext_irq_cb_t callback,
config &= ~(7 << sense_pos);
config |= trigger << (sense_pos);
hri_eic_write_CONFIG_reg(EIC, config_index, config);
// ...set the pin mode...
gpio_set_pin_function(pin, GPIO_PIN_FUNCTION_A);
if (pin == BTN_ALARM || pin == BTN_LIGHT || pin == BTN_MODE) gpio_set_pin_pull_mode(pin, GPIO_PULL_DOWN);
// ...and re-enable the EIC
hri_eic_set_CTRLA_ENABLE_bit(EIC);