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Merge PR #450 - sync after enabling RTC

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According to the data sheet, writing to a Control A register's ENABLE
bit will trigger write synchronization and set SYNCBUSY's ENABLE bit
which will be automatically cleared by the hardware once the write
operation is complete.

It is necessary to wait until SYNCBUSY's ENABLE bit is clear.
Reading synchronized registers before that returns previous values.
Writing synchronized registers before that drops the write and generates
an error value in another register.

The data sheet recommends polling the ENABLE bit in this situation.

Reviewed-by: Matheus Afonso Martins Moreira <matheus@matheusmoreira.com>
GitHub-Pull-Request: https://github.com/joeycastillo/Sensor-Watch/pull/450
References: SAM L22 Family Data Sheet §§ 14.3.2, 14.3.3, 14.3.4, 14.3.5
This commit is contained in:
Matheus Afonso Martins Moreira 2024-08-30 16:20:41 -03:00
parent 879c48ce4d cae5d8a33f
commit fa0cdef45b
1 changed files with 1 additions and 0 deletions
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watch-library/hardware/watch/watch_deepsleep.c
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@ -77,6 +77,7 @@ void watch_register_extwake_callback(uint8_t pin, ext_irq_cb_t callback, bool le
RTC->MODE2.TAMPCTRL.reg = config;
// re-enable the RTC
RTC->MODE2.CTRLA.bit.ENABLE = 1;
while (RTC->MODE2.SYNCBUSY.bit.ENABLE); // wait for RTC to be enabled
NVIC_ClearPendingIRQ(RTC_IRQn);
NVIC_EnableIRQ(RTC_IRQn);