mirror of
https://github.com/firewalkwithm3/Sensor-Watch.git
synced 2024-11-23 03:30:30 +08:00
771 lines
24 KiB
C
771 lines
24 KiB
C
/**
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* \file
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*
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* \brief SAM GCLK
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*
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* Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifdef _SAML22_GCLK_COMPONENT_
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#ifndef _HRI_GCLK_L22_H_INCLUDED_
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#define _HRI_GCLK_L22_H_INCLUDED_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include <hal_atomic.h>
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#if defined(ENABLE_GCLK_CRITICAL_SECTIONS)
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#define GCLK_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
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#define GCLK_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
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#else
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#define GCLK_CRITICAL_SECTION_ENTER()
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#define GCLK_CRITICAL_SECTION_LEAVE()
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#endif
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typedef uint32_t hri_gclk_genctrl_reg_t;
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typedef uint32_t hri_gclk_pchctrl_reg_t;
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typedef uint32_t hri_gclk_syncbusy_reg_t;
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typedef uint8_t hri_gclk_ctrla_reg_t;
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static inline void hri_gclk_wait_for_sync(const void *const hw, hri_gclk_syncbusy_reg_t reg)
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{
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while (((Gclk *)hw)->SYNCBUSY.reg & reg) {
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};
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}
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static inline bool hri_gclk_is_syncing(const void *const hw, hri_gclk_syncbusy_reg_t reg)
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{
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return ((Gclk *)hw)->SYNCBUSY.reg & reg;
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}
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static inline bool hri_gclk_get_SYNCBUSY_SWRST_bit(const void *const hw)
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{
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return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_SWRST) >> GCLK_SYNCBUSY_SWRST_Pos;
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}
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static inline bool hri_gclk_get_SYNCBUSY_GENCTRL0_bit(const void *const hw)
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{
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return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL0) >> GCLK_SYNCBUSY_GENCTRL0_Pos;
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}
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static inline bool hri_gclk_get_SYNCBUSY_GENCTRL1_bit(const void *const hw)
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{
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return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL1) >> GCLK_SYNCBUSY_GENCTRL1_Pos;
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}
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static inline bool hri_gclk_get_SYNCBUSY_GENCTRL2_bit(const void *const hw)
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{
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return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL2) >> GCLK_SYNCBUSY_GENCTRL2_Pos;
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}
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static inline bool hri_gclk_get_SYNCBUSY_GENCTRL3_bit(const void *const hw)
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{
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return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL3) >> GCLK_SYNCBUSY_GENCTRL3_Pos;
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}
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static inline bool hri_gclk_get_SYNCBUSY_GENCTRL4_bit(const void *const hw)
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{
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return (((Gclk *)hw)->SYNCBUSY.reg & GCLK_SYNCBUSY_GENCTRL4) >> GCLK_SYNCBUSY_GENCTRL4_Pos;
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}
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static inline hri_gclk_syncbusy_reg_t hri_gclk_get_SYNCBUSY_reg(const void *const hw, hri_gclk_syncbusy_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Gclk *)hw)->SYNCBUSY.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_gclk_syncbusy_reg_t hri_gclk_read_SYNCBUSY_reg(const void *const hw)
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{
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return ((Gclk *)hw)->SYNCBUSY.reg;
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}
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static inline void hri_gclk_set_CTRLA_SWRST_bit(const void *const hw)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->CTRLA.reg |= GCLK_CTRLA_SWRST;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_gclk_get_CTRLA_SWRST_bit(const void *const hw)
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{
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uint8_t tmp;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
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tmp = ((Gclk *)hw)->CTRLA.reg;
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tmp = (tmp & GCLK_CTRLA_SWRST) >> GCLK_CTRLA_SWRST_Pos;
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return (bool)tmp;
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}
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static inline void hri_gclk_set_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->CTRLA.reg |= mask;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_gclk_ctrla_reg_t hri_gclk_get_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
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{
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uint8_t tmp;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
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tmp = ((Gclk *)hw)->CTRLA.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_gclk_write_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t data)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->CTRLA.reg = data;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_clear_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->CTRLA.reg &= ~mask;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_toggle_CTRLA_reg(const void *const hw, hri_gclk_ctrla_reg_t mask)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->CTRLA.reg ^= mask;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_gclk_ctrla_reg_t hri_gclk_read_CTRLA_reg(const void *const hw)
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{
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_SWRST);
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return ((Gclk *)hw)->CTRLA.reg;
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}
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static inline void hri_gclk_set_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_GENEN;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_gclk_get_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
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{
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uint32_t tmp;
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tmp = ((Gclk *)hw)->GENCTRL[index].reg;
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tmp = (tmp & GCLK_GENCTRL_GENEN) >> GCLK_GENCTRL_GENEN_Pos;
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return (bool)tmp;
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}
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static inline void hri_gclk_write_GENCTRL_GENEN_bit(const void *const hw, uint8_t index, bool value)
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{
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uint32_t tmp;
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GCLK_CRITICAL_SECTION_ENTER();
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tmp = ((Gclk *)hw)->GENCTRL[index].reg;
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tmp &= ~GCLK_GENCTRL_GENEN;
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tmp |= value << GCLK_GENCTRL_GENEN_Pos;
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((Gclk *)hw)->GENCTRL[index].reg = tmp;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_clear_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_GENEN;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_toggle_GENCTRL_GENEN_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_GENEN;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_set_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_IDC;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_gclk_get_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
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{
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uint32_t tmp;
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tmp = ((Gclk *)hw)->GENCTRL[index].reg;
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tmp = (tmp & GCLK_GENCTRL_IDC) >> GCLK_GENCTRL_IDC_Pos;
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return (bool)tmp;
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}
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static inline void hri_gclk_write_GENCTRL_IDC_bit(const void *const hw, uint8_t index, bool value)
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{
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uint32_t tmp;
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GCLK_CRITICAL_SECTION_ENTER();
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tmp = ((Gclk *)hw)->GENCTRL[index].reg;
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tmp &= ~GCLK_GENCTRL_IDC;
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tmp |= value << GCLK_GENCTRL_IDC_Pos;
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((Gclk *)hw)->GENCTRL[index].reg = tmp;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_clear_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_IDC;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_toggle_GENCTRL_IDC_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_IDC;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_set_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OOV;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_gclk_get_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
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{
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uint32_t tmp;
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tmp = ((Gclk *)hw)->GENCTRL[index].reg;
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tmp = (tmp & GCLK_GENCTRL_OOV) >> GCLK_GENCTRL_OOV_Pos;
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return (bool)tmp;
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}
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static inline void hri_gclk_write_GENCTRL_OOV_bit(const void *const hw, uint8_t index, bool value)
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{
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uint32_t tmp;
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GCLK_CRITICAL_SECTION_ENTER();
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tmp = ((Gclk *)hw)->GENCTRL[index].reg;
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tmp &= ~GCLK_GENCTRL_OOV;
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tmp |= value << GCLK_GENCTRL_OOV_Pos;
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((Gclk *)hw)->GENCTRL[index].reg = tmp;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_clear_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OOV;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_toggle_GENCTRL_OOV_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OOV;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_set_GENCTRL_OE_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_OE;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_gclk_get_GENCTRL_OE_bit(const void *const hw, uint8_t index)
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{
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uint32_t tmp;
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tmp = ((Gclk *)hw)->GENCTRL[index].reg;
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tmp = (tmp & GCLK_GENCTRL_OE) >> GCLK_GENCTRL_OE_Pos;
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return (bool)tmp;
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}
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static inline void hri_gclk_write_GENCTRL_OE_bit(const void *const hw, uint8_t index, bool value)
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{
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uint32_t tmp;
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GCLK_CRITICAL_SECTION_ENTER();
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tmp = ((Gclk *)hw)->GENCTRL[index].reg;
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tmp &= ~GCLK_GENCTRL_OE;
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tmp |= value << GCLK_GENCTRL_OE_Pos;
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((Gclk *)hw)->GENCTRL[index].reg = tmp;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_clear_GENCTRL_OE_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_OE;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_toggle_GENCTRL_OE_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_OE;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_set_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIVSEL;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_gclk_get_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
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{
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uint32_t tmp;
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tmp = ((Gclk *)hw)->GENCTRL[index].reg;
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tmp = (tmp & GCLK_GENCTRL_DIVSEL) >> GCLK_GENCTRL_DIVSEL_Pos;
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return (bool)tmp;
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}
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static inline void hri_gclk_write_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index, bool value)
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{
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uint32_t tmp;
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GCLK_CRITICAL_SECTION_ENTER();
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tmp = ((Gclk *)hw)->GENCTRL[index].reg;
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tmp &= ~GCLK_GENCTRL_DIVSEL;
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tmp |= value << GCLK_GENCTRL_DIVSEL_Pos;
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((Gclk *)hw)->GENCTRL[index].reg = tmp;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_clear_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIVSEL;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_toggle_GENCTRL_DIVSEL_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIVSEL;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_gclk_set_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
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{
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GCLK_CRITICAL_SECTION_ENTER();
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((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_RUNSTDBY;
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hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
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GCLK_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_gclk_get_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
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{
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uint32_t tmp;
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tmp = ((Gclk *)hw)->GENCTRL[index].reg;
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tmp = (tmp & GCLK_GENCTRL_RUNSTDBY) >> GCLK_GENCTRL_RUNSTDBY_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_gclk_write_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index, bool value)
|
|
{
|
|
uint32_t tmp;
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
|
|
tmp &= ~GCLK_GENCTRL_RUNSTDBY;
|
|
tmp |= value << GCLK_GENCTRL_RUNSTDBY_Pos;
|
|
((Gclk *)hw)->GENCTRL[index].reg = tmp;
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_clear_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_RUNSTDBY;
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_toggle_GENCTRL_RUNSTDBY_bit(const void *const hw, uint8_t index)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_RUNSTDBY;
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_set_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_SRC(mask);
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_SRC_bf(const void *const hw, uint8_t index,
|
|
hri_gclk_genctrl_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
|
|
tmp = (tmp & GCLK_GENCTRL_SRC(mask)) >> GCLK_GENCTRL_SRC_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_gclk_write_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
|
|
tmp &= ~GCLK_GENCTRL_SRC_Msk;
|
|
tmp |= GCLK_GENCTRL_SRC(data);
|
|
((Gclk *)hw)->GENCTRL[index].reg = tmp;
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_clear_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_SRC(mask);
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_toggle_GENCTRL_SRC_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_SRC(mask);
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_SRC_bf(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
|
|
tmp = (tmp & GCLK_GENCTRL_SRC_Msk) >> GCLK_GENCTRL_SRC_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_gclk_set_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->GENCTRL[index].reg |= GCLK_GENCTRL_DIV(mask);
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_DIV_bf(const void *const hw, uint8_t index,
|
|
hri_gclk_genctrl_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
|
|
tmp = (tmp & GCLK_GENCTRL_DIV(mask)) >> GCLK_GENCTRL_DIV_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_gclk_write_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
|
|
tmp &= ~GCLK_GENCTRL_DIV_Msk;
|
|
tmp |= GCLK_GENCTRL_DIV(data);
|
|
((Gclk *)hw)->GENCTRL[index].reg = tmp;
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_clear_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->GENCTRL[index].reg &= ~GCLK_GENCTRL_DIV(mask);
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_toggle_GENCTRL_DIV_bf(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->GENCTRL[index].reg ^= GCLK_GENCTRL_DIV(mask);
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_DIV_bf(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
|
|
tmp = (tmp & GCLK_GENCTRL_DIV_Msk) >> GCLK_GENCTRL_DIV_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_gclk_set_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->GENCTRL[index].reg |= mask;
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_gclk_genctrl_reg_t hri_gclk_get_GENCTRL_reg(const void *const hw, uint8_t index,
|
|
hri_gclk_genctrl_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
tmp = ((Gclk *)hw)->GENCTRL[index].reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_gclk_write_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t data)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->GENCTRL[index].reg = data;
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_clear_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->GENCTRL[index].reg &= ~mask;
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_toggle_GENCTRL_reg(const void *const hw, uint8_t index, hri_gclk_genctrl_reg_t mask)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->GENCTRL[index].reg ^= mask;
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_gclk_genctrl_reg_t hri_gclk_read_GENCTRL_reg(const void *const hw, uint8_t index)
|
|
{
|
|
hri_gclk_wait_for_sync(hw, GCLK_SYNCBUSY_MASK);
|
|
return ((Gclk *)hw)->GENCTRL[index].reg;
|
|
}
|
|
|
|
static inline void hri_gclk_set_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_CHEN;
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_gclk_get_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
|
|
tmp = (tmp & GCLK_PCHCTRL_CHEN) >> GCLK_PCHCTRL_CHEN_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_gclk_write_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index, bool value)
|
|
{
|
|
uint32_t tmp;
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
|
|
tmp &= ~GCLK_PCHCTRL_CHEN;
|
|
tmp |= value << GCLK_PCHCTRL_CHEN_Pos;
|
|
((Gclk *)hw)->PCHCTRL[index].reg = tmp;
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_clear_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_CHEN;
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_toggle_PCHCTRL_CHEN_bit(const void *const hw, uint8_t index)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_CHEN;
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_set_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_WRTLOCK;
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline bool hri_gclk_get_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
|
|
tmp = (tmp & GCLK_PCHCTRL_WRTLOCK) >> GCLK_PCHCTRL_WRTLOCK_Pos;
|
|
return (bool)tmp;
|
|
}
|
|
|
|
static inline void hri_gclk_write_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index, bool value)
|
|
{
|
|
uint32_t tmp;
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
|
|
tmp &= ~GCLK_PCHCTRL_WRTLOCK;
|
|
tmp |= value << GCLK_PCHCTRL_WRTLOCK_Pos;
|
|
((Gclk *)hw)->PCHCTRL[index].reg = tmp;
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_clear_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_WRTLOCK;
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_toggle_PCHCTRL_WRTLOCK_bit(const void *const hw, uint8_t index)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_WRTLOCK;
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_set_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->PCHCTRL[index].reg |= GCLK_PCHCTRL_GEN(mask);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_GEN_bf(const void *const hw, uint8_t index,
|
|
hri_gclk_pchctrl_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
|
|
tmp = (tmp & GCLK_PCHCTRL_GEN(mask)) >> GCLK_PCHCTRL_GEN_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_gclk_write_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
|
|
{
|
|
uint32_t tmp;
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
|
|
tmp &= ~GCLK_PCHCTRL_GEN_Msk;
|
|
tmp |= GCLK_PCHCTRL_GEN(data);
|
|
((Gclk *)hw)->PCHCTRL[index].reg = tmp;
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_clear_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->PCHCTRL[index].reg &= ~GCLK_PCHCTRL_GEN(mask);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_toggle_PCHCTRL_GEN_bf(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->PCHCTRL[index].reg ^= GCLK_PCHCTRL_GEN(mask);
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_GEN_bf(const void *const hw, uint8_t index)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
|
|
tmp = (tmp & GCLK_PCHCTRL_GEN_Msk) >> GCLK_PCHCTRL_GEN_Pos;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_gclk_set_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->PCHCTRL[index].reg |= mask;
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_gclk_pchctrl_reg_t hri_gclk_get_PCHCTRL_reg(const void *const hw, uint8_t index,
|
|
hri_gclk_pchctrl_reg_t mask)
|
|
{
|
|
uint32_t tmp;
|
|
tmp = ((Gclk *)hw)->PCHCTRL[index].reg;
|
|
tmp &= mask;
|
|
return tmp;
|
|
}
|
|
|
|
static inline void hri_gclk_write_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t data)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->PCHCTRL[index].reg = data;
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_clear_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->PCHCTRL[index].reg &= ~mask;
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline void hri_gclk_toggle_PCHCTRL_reg(const void *const hw, uint8_t index, hri_gclk_pchctrl_reg_t mask)
|
|
{
|
|
GCLK_CRITICAL_SECTION_ENTER();
|
|
((Gclk *)hw)->PCHCTRL[index].reg ^= mask;
|
|
GCLK_CRITICAL_SECTION_LEAVE();
|
|
}
|
|
|
|
static inline hri_gclk_pchctrl_reg_t hri_gclk_read_PCHCTRL_reg(const void *const hw, uint8_t index)
|
|
{
|
|
return ((Gclk *)hw)->PCHCTRL[index].reg;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|
|
|
|
#endif /* _HRI_GCLK_L22_H_INCLUDED */
|
|
#endif /* _SAML22_GCLK_COMPONENT_ */
|