mirror of
https://github.com/firewalkwithm3/Sensor-Watch.git
synced 2024-11-23 03:30:30 +08:00
465 lines
13 KiB
C
465 lines
13 KiB
C
/**
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* \file
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*
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* \brief SAM FREQM
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*
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* Copyright (c) 2017-2018 Microchip Technology Inc. and its subsidiaries.
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*
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* \asf_license_start
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*
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* \page License
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*
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* Subject to your compliance with these terms, you may use Microchip
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* software and any derivatives exclusively with Microchip products.
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* It is your responsibility to comply with third party license terms applicable
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* to your use of third party software (including open source software) that
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* may accompany Microchip software.
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*
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* THIS SOFTWARE IS SUPPLIED BY MICROCHIP "AS IS". NO WARRANTIES,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, APPLY TO THIS SOFTWARE,
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* INCLUDING ANY IMPLIED WARRANTIES OF NON-INFRINGEMENT, MERCHANTABILITY,
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* AND FITNESS FOR A PARTICULAR PURPOSE. IN NO EVENT WILL MICROCHIP BE
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* LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL OR CONSEQUENTIAL
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* LOSS, DAMAGE, COST OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE
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* SOFTWARE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE
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* POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT
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* ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY
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* RELATED TO THIS SOFTWARE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY,
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* THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THIS SOFTWARE.
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*
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* \asf_license_stop
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*
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*/
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#ifdef _SAML22_FREQM_COMPONENT_
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#ifndef _HRI_FREQM_L22_H_INCLUDED_
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#define _HRI_FREQM_L22_H_INCLUDED_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdbool.h>
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#include <hal_atomic.h>
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#if defined(ENABLE_FREQM_CRITICAL_SECTIONS)
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#define FREQM_CRITICAL_SECTION_ENTER() CRITICAL_SECTION_ENTER()
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#define FREQM_CRITICAL_SECTION_LEAVE() CRITICAL_SECTION_LEAVE()
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#else
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#define FREQM_CRITICAL_SECTION_ENTER()
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#define FREQM_CRITICAL_SECTION_LEAVE()
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#endif
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typedef uint16_t hri_freqm_cfga_reg_t;
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typedef uint32_t hri_freqm_syncbusy_reg_t;
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typedef uint32_t hri_freqm_value_reg_t;
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typedef uint8_t hri_freqm_ctrla_reg_t;
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typedef uint8_t hri_freqm_ctrlb_reg_t;
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typedef uint8_t hri_freqm_intenset_reg_t;
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typedef uint8_t hri_freqm_intflag_reg_t;
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typedef uint8_t hri_freqm_status_reg_t;
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static inline void hri_freqm_wait_for_sync(const void *const hw, hri_freqm_syncbusy_reg_t reg)
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{
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while (((Freqm *)hw)->SYNCBUSY.reg & reg) {
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};
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}
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static inline bool hri_freqm_is_syncing(const void *const hw, hri_freqm_syncbusy_reg_t reg)
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{
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return ((Freqm *)hw)->SYNCBUSY.reg & reg;
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}
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static inline bool hri_freqm_get_INTFLAG_DONE_bit(const void *const hw)
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{
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return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos;
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}
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static inline void hri_freqm_clear_INTFLAG_DONE_bit(const void *const hw)
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{
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((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE;
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}
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static inline bool hri_freqm_get_interrupt_DONE_bit(const void *const hw)
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{
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return (((Freqm *)hw)->INTFLAG.reg & FREQM_INTFLAG_DONE) >> FREQM_INTFLAG_DONE_Pos;
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}
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static inline void hri_freqm_clear_interrupt_DONE_bit(const void *const hw)
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{
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((Freqm *)hw)->INTFLAG.reg = FREQM_INTFLAG_DONE;
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}
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static inline hri_freqm_intflag_reg_t hri_freqm_get_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask)
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{
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uint8_t tmp;
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tmp = ((Freqm *)hw)->INTFLAG.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_freqm_intflag_reg_t hri_freqm_read_INTFLAG_reg(const void *const hw)
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{
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return ((Freqm *)hw)->INTFLAG.reg;
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}
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static inline void hri_freqm_clear_INTFLAG_reg(const void *const hw, hri_freqm_intflag_reg_t mask)
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{
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((Freqm *)hw)->INTFLAG.reg = mask;
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}
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static inline void hri_freqm_set_INTEN_DONE_bit(const void *const hw)
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{
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((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE;
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}
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static inline bool hri_freqm_get_INTEN_DONE_bit(const void *const hw)
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{
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return (((Freqm *)hw)->INTENSET.reg & FREQM_INTENSET_DONE) >> FREQM_INTENSET_DONE_Pos;
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}
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static inline void hri_freqm_write_INTEN_DONE_bit(const void *const hw, bool value)
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{
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if (value == 0x0) {
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((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE;
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} else {
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((Freqm *)hw)->INTENSET.reg = FREQM_INTENSET_DONE;
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}
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}
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static inline void hri_freqm_clear_INTEN_DONE_bit(const void *const hw)
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{
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((Freqm *)hw)->INTENCLR.reg = FREQM_INTENSET_DONE;
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}
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static inline void hri_freqm_set_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
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{
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((Freqm *)hw)->INTENSET.reg = mask;
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}
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static inline hri_freqm_intenset_reg_t hri_freqm_get_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
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{
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uint8_t tmp;
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tmp = ((Freqm *)hw)->INTENSET.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_freqm_intenset_reg_t hri_freqm_read_INTEN_reg(const void *const hw)
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{
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return ((Freqm *)hw)->INTENSET.reg;
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}
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static inline void hri_freqm_write_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t data)
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{
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((Freqm *)hw)->INTENSET.reg = data;
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((Freqm *)hw)->INTENCLR.reg = ~data;
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}
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static inline void hri_freqm_clear_INTEN_reg(const void *const hw, hri_freqm_intenset_reg_t mask)
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{
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((Freqm *)hw)->INTENCLR.reg = mask;
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}
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static inline bool hri_freqm_get_SYNCBUSY_SWRST_bit(const void *const hw)
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{
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return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_SWRST) >> FREQM_SYNCBUSY_SWRST_Pos;
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}
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static inline bool hri_freqm_get_SYNCBUSY_ENABLE_bit(const void *const hw)
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{
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return (((Freqm *)hw)->SYNCBUSY.reg & FREQM_SYNCBUSY_ENABLE) >> FREQM_SYNCBUSY_ENABLE_Pos;
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}
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static inline hri_freqm_syncbusy_reg_t hri_freqm_get_SYNCBUSY_reg(const void *const hw, hri_freqm_syncbusy_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Freqm *)hw)->SYNCBUSY.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_freqm_syncbusy_reg_t hri_freqm_read_SYNCBUSY_reg(const void *const hw)
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{
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return ((Freqm *)hw)->SYNCBUSY.reg;
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}
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static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_VALUE_bf(const void *const hw, hri_freqm_value_reg_t mask)
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{
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return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE(mask)) >> FREQM_VALUE_VALUE_Pos;
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}
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static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_VALUE_bf(const void *const hw)
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{
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return (((Freqm *)hw)->VALUE.reg & FREQM_VALUE_VALUE_Msk) >> FREQM_VALUE_VALUE_Pos;
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}
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static inline hri_freqm_value_reg_t hri_freqm_get_VALUE_reg(const void *const hw, hri_freqm_value_reg_t mask)
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{
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uint32_t tmp;
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tmp = ((Freqm *)hw)->VALUE.reg;
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tmp &= mask;
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return tmp;
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}
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static inline hri_freqm_value_reg_t hri_freqm_read_VALUE_reg(const void *const hw)
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{
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return ((Freqm *)hw)->VALUE.reg;
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}
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static inline void hri_freqm_set_CTRLA_SWRST_bit(const void *const hw)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_SWRST;
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hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST);
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_freqm_get_CTRLA_SWRST_bit(const void *const hw)
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{
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uint8_t tmp;
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hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST);
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tmp = ((Freqm *)hw)->CTRLA.reg;
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tmp = (tmp & FREQM_CTRLA_SWRST) >> FREQM_CTRLA_SWRST_Pos;
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return (bool)tmp;
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}
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static inline void hri_freqm_set_CTRLA_ENABLE_bit(const void *const hw)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CTRLA.reg |= FREQM_CTRLA_ENABLE;
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hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_freqm_get_CTRLA_ENABLE_bit(const void *const hw)
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{
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uint8_t tmp;
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hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
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tmp = ((Freqm *)hw)->CTRLA.reg;
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tmp = (tmp & FREQM_CTRLA_ENABLE) >> FREQM_CTRLA_ENABLE_Pos;
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return (bool)tmp;
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}
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static inline void hri_freqm_write_CTRLA_ENABLE_bit(const void *const hw, bool value)
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{
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uint8_t tmp;
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FREQM_CRITICAL_SECTION_ENTER();
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tmp = ((Freqm *)hw)->CTRLA.reg;
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tmp &= ~FREQM_CTRLA_ENABLE;
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tmp |= value << FREQM_CTRLA_ENABLE_Pos;
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((Freqm *)hw)->CTRLA.reg = tmp;
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hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_freqm_clear_CTRLA_ENABLE_bit(const void *const hw)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CTRLA.reg &= ~FREQM_CTRLA_ENABLE;
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hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_freqm_toggle_CTRLA_ENABLE_bit(const void *const hw)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CTRLA.reg ^= FREQM_CTRLA_ENABLE;
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hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_SWRST | FREQM_SYNCBUSY_ENABLE);
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_freqm_set_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CTRLA.reg |= mask;
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hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_freqm_ctrla_reg_t hri_freqm_get_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
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{
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uint8_t tmp;
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hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
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tmp = ((Freqm *)hw)->CTRLA.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_freqm_write_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t data)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CTRLA.reg = data;
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hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_freqm_clear_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CTRLA.reg &= ~mask;
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hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_freqm_toggle_CTRLA_reg(const void *const hw, hri_freqm_ctrla_reg_t mask)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CTRLA.reg ^= mask;
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hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_freqm_ctrla_reg_t hri_freqm_read_CTRLA_reg(const void *const hw)
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{
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hri_freqm_wait_for_sync(hw, FREQM_SYNCBUSY_MASK);
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return ((Freqm *)hw)->CTRLA.reg;
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}
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static inline void hri_freqm_set_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CFGA.reg |= FREQM_CFGA_REFNUM(mask);
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
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{
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uint16_t tmp;
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tmp = ((Freqm *)hw)->CFGA.reg;
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tmp = (tmp & FREQM_CFGA_REFNUM(mask)) >> FREQM_CFGA_REFNUM_Pos;
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return tmp;
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}
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static inline void hri_freqm_write_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t data)
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{
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uint16_t tmp;
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FREQM_CRITICAL_SECTION_ENTER();
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tmp = ((Freqm *)hw)->CFGA.reg;
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tmp &= ~FREQM_CFGA_REFNUM_Msk;
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tmp |= FREQM_CFGA_REFNUM(data);
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((Freqm *)hw)->CFGA.reg = tmp;
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_freqm_clear_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CFGA.reg &= ~FREQM_CFGA_REFNUM(mask);
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_freqm_toggle_CFGA_REFNUM_bf(const void *const hw, hri_freqm_cfga_reg_t mask)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CFGA.reg ^= FREQM_CFGA_REFNUM(mask);
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_REFNUM_bf(const void *const hw)
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{
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uint16_t tmp;
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tmp = ((Freqm *)hw)->CFGA.reg;
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tmp = (tmp & FREQM_CFGA_REFNUM_Msk) >> FREQM_CFGA_REFNUM_Pos;
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return tmp;
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}
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static inline void hri_freqm_set_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CFGA.reg |= mask;
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_freqm_cfga_reg_t hri_freqm_get_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
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{
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uint16_t tmp;
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tmp = ((Freqm *)hw)->CFGA.reg;
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tmp &= mask;
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return tmp;
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}
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static inline void hri_freqm_write_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t data)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CFGA.reg = data;
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_freqm_clear_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CFGA.reg &= ~mask;
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline void hri_freqm_toggle_CFGA_reg(const void *const hw, hri_freqm_cfga_reg_t mask)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CFGA.reg ^= mask;
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_freqm_cfga_reg_t hri_freqm_read_CFGA_reg(const void *const hw)
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{
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return ((Freqm *)hw)->CFGA.reg;
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}
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static inline bool hri_freqm_get_STATUS_BUSY_bit(const void *const hw)
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{
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return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_BUSY) >> FREQM_STATUS_BUSY_Pos;
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}
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static inline void hri_freqm_clear_STATUS_BUSY_bit(const void *const hw)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->STATUS.reg = FREQM_STATUS_BUSY;
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline bool hri_freqm_get_STATUS_OVF_bit(const void *const hw)
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{
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return (((Freqm *)hw)->STATUS.reg & FREQM_STATUS_OVF) >> FREQM_STATUS_OVF_Pos;
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}
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static inline void hri_freqm_clear_STATUS_OVF_bit(const void *const hw)
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{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->STATUS.reg = FREQM_STATUS_OVF;
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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static inline hri_freqm_status_reg_t hri_freqm_get_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask)
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|
{
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uint8_t tmp;
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tmp = ((Freqm *)hw)->STATUS.reg;
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tmp &= mask;
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return tmp;
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}
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|
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static inline void hri_freqm_clear_STATUS_reg(const void *const hw, hri_freqm_status_reg_t mask)
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|
{
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|
FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->STATUS.reg = mask;
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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|
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static inline hri_freqm_status_reg_t hri_freqm_read_STATUS_reg(const void *const hw)
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|
{
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|
return ((Freqm *)hw)->STATUS.reg;
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|
}
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|
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static inline void hri_freqm_write_CTRLB_reg(const void *const hw, hri_freqm_ctrlb_reg_t data)
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|
{
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FREQM_CRITICAL_SECTION_ENTER();
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((Freqm *)hw)->CTRLB.reg = data;
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FREQM_CRITICAL_SECTION_LEAVE();
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}
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|
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#ifdef __cplusplus
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}
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#endif
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|
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#endif /* _HRI_FREQM_L22_H_INCLUDED */
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#endif /* _SAML22_FREQM_COMPONENT_ */
|